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74LVCH8T245BQ,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 12 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
Table 12. Dynamic characteristics for temperature range 40 C to +125 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
V
CC(A)
= 1.5 V 0.1 V
t
pd
propagation
delay
An to Bn 1.7 32 1.7 27 1.3 21 1.0 18 0.8 16 ns
Bn to An 0.9 32 0.9 30 0.8 28 0.7 28 0.7 26 ns
t
dis
disable time OE to An 1.5 34 1.5 34 1.5 34 1.5 34 1.4 34 ns
OE
to Bn 2.4 41 2.4 40 1.9 18 1.7 17 1.3 15 ns
t
en
enable time OE to An 0.4 40 0.4 40 0.4 40 0.4 40 0.4 40 ns
OE
to Bn 1.8 43 1.8 41 1.5 22 1.2 18 0.9 16 ns
V
CC(A)
= 1.8 V 0.15 V
t
pd
propagation
delay
An to Bn 1.7 30 1.7 25.9 1.3 13.2 1.0 11.4 0.8 11.1 ns
Bn to An 0.9 27 0.9 28.8 0.8 27.6 0.7 27.4 0.7 27.4 ns
t
dis
disable time OE to An 1.5 34 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 ns
OE
to Bn 2.4 40 2.4 36.2 1.9 17.1 1.7 16.0 1.3 14.3 ns
t
en
enable time OE to An 0.4 28 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 ns
OE
to Bn 1.8 41 1.8 40 1.5 20 1.2 16.6 0.9 14.8 ns
V
CC(A)
= 2.5 V 0.2 V
t
pd
propagation
delay
An to Bn 1.5 28 1.5 25.4 1.2 13 0.8 10.2 0.6 8.8 ns
Bn to An 1.2 23 1.2 13.3 1.0 13.1 1.0 12.9 0.9 12.8 ns
t
dis
disable time OE to An 1.4 13 1.4 13 1.4 13 1.4 13 1.4 13 ns
OE
to Bn 2.3 37 2.3 33.6 1.8 15 1.7 14.3 0.9 10.9 ns
t
en
enable time OE to An 1.0 17.2 1.0 17.2 1.0 17.3 1.0 17.2 1.0 17.3 ns
OE
to Bn 1.7 38 1.7 32.2 1.5 18.1 1.2 14.1 1.0 11.2 ns
V
CC(A)
= 3.3 V 0.3 V
t
pd
propagation
delay
An to Bn 1.5 28 1.5 25.2 1.1 12.8 0.8 10.3 0.5 10.4 ns
Bn to An 0.8 18 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns
t
dis
disable time OE to An 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 ns
OE
to Bn 2.1 36 2.1 33 1.7 14.3 1.5 12.6 0.8 10.3 ns
t
en
enable time OE to An 0.8 14.1 0.8 14.1 0.8 13.6 0.8 13.2 0.8 13.6 ns
OE
to Bn 1.8 37 1.8 31.7 1.4 18.4 1.1 12.9 0.9 10.9 ns
V
CC(A)
= 5.0 V 0.5 V
t
pd
propagation
delay
An to Bn 1.5 26 1.5 25.4 1.0 12.8 0.7 10 0.4 8.2 ns
Bn to An 0.7 16 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 ns
t
dis
disable time OE to An 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 ns
OE
to Bn 2.0 36 2.0 32.7 1.6 13.7 1.4 12 0.7 9.7 ns
t
en
enable time OE to An 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 ns
OE
to Bn 1.5 37 1.5 31.6 1.3 18.4 1.0 13.7 0.9 10.7 ns
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 13 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
11. Waveforms
[1] V
CCI
is the supply voltage associated with the data input port.
[2] V
CCO
is the supply voltage associated with the output port.
Measurement points are given in Table 13
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times
001aai475
V
M
V
M
V
I
An, Bn input
GND
V
OH
Bn, An output
V
OL
t
PHL
t
PLH
Measurement points are given in Table 13.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
001aai474
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
OL
V
OH
V
CCO
V
I
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 13. Measurement points
Supply voltage Input
[1]
Output
[2]
V
CC(A)
, V
CC(B)
V
M
V
M
V
X
V
Y
1.2 V to 1.6 V 0.5V
CCI
0.5V
CCO
V
OL
+0.1V V
OH
0.1 V
1.65 V to 2.7 V 0.5V
CCI
0.5V
CCO
V
OL
+0.15V V
OH
0.15 V
3.0 V to 5.5 V 0.5V
CCI
0.5V
CCO
V
OL
+0.3V V
OH
0.3 V
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 14 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] V
CCI
is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns.
[3] V
CCO
is the supply voltage associated with the output port.
Test data is given in Table 14
.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance.
V
EXT
= External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 14. Test data
Supply voltage Input Load V
EXT
V
CC(A)
, V
CC(B)
V
I
[1]
t/V
[2]
C
L
R
L
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
[3]
1.2 V to 5.5 V V
CCI
1.0ns/V 15pF 2k open GND 2V
CCO
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

74LVCH8T245BQ,118

Mfr. #:
Buy 74LVCH8T245BQ,118
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 8-BIT DUAL SUPPLY TRANSLATING XCVR 3-S
Lifecycle:
New from this manufacturer.
Delivery:
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