Document #: 38-05460 Rev. *G Page 5 of 13
Switching Characteristics
Over the Operating Range
[5]
Parameter Description
-10 (Ind’l/Auto-A)
UnitMin. Max.
Read Cycle
t
power
[6]
V
CC
(typical) to the first access 100 s
t
RC
Read cycle time 10 ns
t
AA
Address to data valid 10 ns
t
OHA
Data hold from address change 3 ns
t
ACE
CE LOW to data valid 10 ns
t
DOE
OE LOW to data valid 5 ns
t
LZOE
OE LOW to low-Z
[8]
0ns
t
HZOE
OE HIGH to high-Z
[7, 8]
5ns
t
LZCE
CE LOW to low-Z
[8]
3ns
t
HZCE
CE HIGH to high-Z
[7, 8]
5ns
t
PU
[9]
CE LOW to power-up 0 ns
t
PD
[9]
CE HIGH to power-down 10 ns
t
DBE
Byte Enable to data valid 5 ns
t
LZBE
Byte Enable to low-Z 0 ns
t
HZBE
Byte Disable to high-Z 6 ns
Write Cycle
[10]
t
WC
Write cycle time 10 ns
t
SCE
CE LOW to write end 8 ns
t
AW
Address set-up to write end 8 ns
t
HA
Address hold from write end 0 ns
t
SA
Address set-up to write start 0 ns
t
PWE
WE pulse width 7 ns
t
SD
Data set-up to write end 5 ns
t
HD
Data hold from write end 0 ns
t
LZWE
WE HIGH to low-Z
[8]
3ns
t
HZWE
WE LOW to high-Z
[7, 8]
5ns
t
BW
Byte enable to end of write 7 ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. This parameter is guaranteed by design and is not tested.
10.The internal Write time of the memory is defined by the overlap of CE
LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
