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AD5300BRTZ-500RL7

P1-P3P4-P6P7-P9P10-P12P13-P14
AD5300
–9–
REV.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
Figure 24. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 2.5 µs for V
DD
= 5 V and 5 µs for
V
DD
= 3 V (see Figure 18).
MICROPROCESSOR INTERFACING
AD5300 to ADSP-2101/ADSP-2103 Interface
Figure 25 shows a serial interface between the AD5300 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
ADSP-2101/
ADSP-2103*
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
SCLK
AD5300*
TFS
SCLK
Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface
DB15
DB0
SCLK
SYNC
DIN
DB15
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
FALLING EDGE
Figure 23.
SYNC
Interrupt Facility
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid; neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 23.
Power-On Reset
The AD5300 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
zeros and the output voltage is 0 V. It remains there until
a valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the out-
put of the DAC while it is in the process of powering up.
Power-Down Modes
The AD5300 contains four separate modes of operation. These
modes are software programmable by setting two bits (DB13
and DB12) in the control register. Table I shows how the state
of the bits corresponds to the mode of operation of the device.
Table I. Modes of Operation for the AD5300
DB13 DB12 Operating Mode
00 Normal Operation
Power-Down Modes
01 1 kΩ to GND
10 100 kΩ to GND
11 Three-State
When both bits are set to 0, the part works normally with its
normal power consumption of 140 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has an
advantage: the output impedance of the part is known while the
part is in power-down mode. There are three different options.
The output is connected internally to GND through a 1 kΩ resis-
tor or a 100 kΩ resistor, or it is left open-circuited (three-stated).
The output stage is illustrated in Figure 24.
D
AD5300
–10–
REV.
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
AD5300*
SCLK
MICROWIRE*
SK
SO
CS
Figure 28. AD5300 to MICROWIRE Interface
APPLICATIONS
Using REF19x as a Power Supply for AD5300
Because the supply current required by the AD5300 is extremely
low, an alternative option is to use a REF19x voltage reference
(REF195 for 5 V or REF193 for 3 V) to supply the required
voltage to the part—see Figure 29. This is especially useful if
your power supply is quite noisy or if the system supply voltages
are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x
will output a steady supply voltage for the AD5300. If the low
dropout REF195 is used, the current it needs to supply to the
AD5300 is 140 µA. This is with no load on the output of the
DAC. When the DAC output is loaded, the REF195 also needs to
supply the current to the load. The total current required (with
a 5 kΩ load on the DAC output) is
140 µA + (5 V/5 kΩ) = 1.14 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.3 ppm (11.5 µV) for the 1.14 mA
current drawn from it. This corresponds to a 0.0006 LSB error.
AD5300
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
15V
5V
140␮A
V
OUT
= 0V TO 5V
REF195
Figure 29. REF195 as Power Supply to AD5300
Bipolar Operation Using the AD5300
The AD5300 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 30. The circuit in Figure 30 will give an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
VV
DRR
R
V
R
R
ODD DD
=×
×
+
×
256
12
1
2
1
–
where D represents the input code in decimal (0 to 255).
With V
DD
= 5 V, R1 = R2 = 10 kΩ,
V
O
=
10 × D
256
–5V
This is an output voltage range of ±5 V with 00 Hex corresponding
to a –5 V output and FF Hex corresponding to a 5 V output.
AD5300 to 68HC11/68L11 Interface
Figure 26 shows a serial interface between the AD5300 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5300, while the MOSI output drives
the serial data line of the DAC. The SYNC signal is derived
from a port line (PC7). The setup conditions for correct opera-
tion of this interface are as follows: the 68HC11/68L11 should
be configured so that its CPOL bit is a 0 and its CPHA bit is a
1. When data is being transmitted to the DAC, the SYNC line is
taken low (PC7). When the 68HC11/68L11 is configured as
above, data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11/68L11 is transmit-
ted in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. In order to
load data to the AD5300, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC and PC7 is taken high at the end of this procedure.
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
AD5300*
SCLK
68HC11/68L11*
SCK
MOSI
PC7
Figure 26. AD5300 to 68HC11/68L11 Interface
AD5300 to 80C51/80L51 Interface
Figure 27 shows a serial interface between the AD5300 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5300,
while RXD drives the serial data line of the part. The SYNC
signal is again derived from a bit programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5300, P3.3 is taken low. The 80C51/80L51 transmits
data only in 8-bit bytes; thus, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5300 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine takes this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
AD5300*
SCLK
80C51/80L51*
TXD
RXD
P3.3
Figure 27. AD5300 to 80C51/80L51 Interface
AD5300 to MICROWIRE Interface
Figure 28 shows an interface between the AD5300 and any
MICROWIRE compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the AD5300 on
the rising edge of the SK.
D
AD5300
–11–
REV.
0.1␮F
V
DD
10k⍀
POWER
10␮F
V
DD
SYNC
SCLK
DATA
AD5300
5V
REGULATOR
V
DD
10k⍀
V
DD
10k⍀
V
OUT
DIN
SYNC
SCLK
GND
Figure 32. AD5300 with an Opto-Isolated Interface
Power Supply Bypassing and Grounding
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5300 should
have separate analog and digital sections, each having its own
area of the board. If the AD5300 is in a system where other
devices require an AGND to DGND connection, the connec-
tion should be made at one point only. This ground point should
be as close as possible to the AD5300.
The power supply to the AD5300 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physi-
cally as close as possible to the device with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor
has low effective series resistance (ESR) and effective series
inductance (ESI), e.g., common ceramic types of capacitors. This
0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as pos-
sible to provide a low impedance path and reduce glitch effects
on the supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique where the component side of the board
is dedicated to the ground plane only and the signal traces are
placed on the solder side. However, this is not always possible
with a 2-layer board.
R2 = 10k⍀
+5V
–5V
AD820/
OP295
3-WIRE
SERIAL
INTERFACE
+5V
AD5300
10␮F
0.1␮F
V
DD
V
OUT
R1 = 10k⍀
ⴞ5V
Figure 30. Bipolar Operation with the AD5300
Two 8-Bit AD5300s Together Make One 15-Bit DAC
By using the configuration in Figure 31, it can be seen that one
15-bit DAC can be made with two 8-bit AD5300s. Because of
the low supply current the AD5300 requires, the output of one
DAC may be directed into the supply pin of the second DAC.
The first DAC has no problem sourcing the required 140 µA
of current for the second DAC.
Since the AD5300 works on any supply voltage between 2.5 V
and 5.5 V, the output of the first DAC can be anywhere above
2.5 V. For a V
DD
of 5 V, this allows the first DAC to use half of
its output range (2.5 V to 5 V), which gives 7-bit resolution on
the output voltage. This output then becomes the supply and
reference for the second DAC. The second DAC has 8-bit reso-
lution on the output range, which gives an overall resolution for
the system of 15 bits.
A level-shifter is required to ensure that the logic input voltages
do not exceed the supply voltage of the part. The microcontroller
outputs 5 V signals, which need to be level shifted down to 2.5 V
in the case of the second DAC having a supply of only 2.5 V.
5V
MICRO-
CONTROLLER
V
OUT
= 2.5V TO 5V
LEVEL
SHIFTER
V
OUT
= 0V TO 5V
15-BIT
RESOLUTION
SYNC
SCLK
DIN
V
DD
AD5300
AD5300
V
DD
SYNC
SCLK
DIN
Figure 31. 15-Bit DAC Using Two AD5300s
Using AD5300 with an Opto-Isolated Interface
In process-control applications in industrial environments, it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5300 uses a 3-wire serial logic interface, it
requires only three opto-isolators to provide the required isola-
tion (see Figure 32). The power supply to the part also needs to
be isolated. This is done by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5300.
D
P1-P3P4-P6P7-P9P10-P12P13-P14

AD5300BRTZ-500RL7

Mfr. #:
Buy AD5300BRTZ-500RL7
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC RR VTG Output 8-Bit IC
Lifecycle:
New from this manufacturer.
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