AD5300BRTZ-500RL7

AD5300
–3–
REV.
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter V
DD
= 2.7 V to 3.6 V V
DD
= 3.6 V to 5.5 V Unit Conditions/Comments
t
1
3
50 33 ns min SCLK Cycle Time
t
2
13 13 ns min SCLK High Time
t
3
22.5 13 ns min SCLK Low Time
t
4
13 13 ns min SYNC to SCLK Falling Edge Setup Time
t
5
55ns min Data Setup Time
t
6
4.5 4.5 ns min Data Hold Time
t
7
00ns min SCLK Falling Edge to SYNC Rising Edge
t
8
50 33 ns min Minimum SYNC High Time
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
See Figure 1.
3
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t
8
DB15
DB0
t
4
t
3
t
2
t
7
t
5
t
6
t
1
Figure 1. Serial Write Operation
(V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
MSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
D
AD5300
–4–
REV.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
OUT
GND
V
DD
SYNC
SCLK
DIN
AD5300
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
NC
AD5300
SYNC
V
OUT
GND
V
DD
SCLK
DIN
NC
NC = NO CONNECT
SOT-23
MSOP
PIN FUNCTION DESCRIPTIONS
SOT-23 MSOP
Pin No. Pin No. Mnemonic Function
14V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
28GND Ground Reference Point for All Circuitry on the Part.
31V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V
DD
should be decoupled
to GND.
47DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
56SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 30 MHz.
65SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the
input data. When SYNC goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless
SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the DAC.
NC 2, 3 NC No Connect.
D
AD5300
–5–
REV.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 2.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 3.
Zero-Code Error
Zero-code error is a measure of the output error when zero code
(00 Hex) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5300 because the output of the DAC cannot go below 0 V.
This is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in LSBs. A
plot of zero-code error vs. temperature can be seen in Figure 6.
Full-Scale Error
Full-scale error is a measure of the output error when full-
scale code (FF Hex) is loaded to the DAC register. Ideally,
the output should be V
DD
– 1 LSB. Full-scale error is expressed
in LSBs. A plot of full-scale error vs. temperature can be
seen in Figure 6.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
taking into account all the various errors. A typical TUE vs.
code plot can be seen in Figure 4.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-secs
and is measured when the digital input code is changed by
1 LSB at the major carry transition (7F Hex to 80 Hex). See
Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is
specified in nV-secs and is measured with a full-scale code
change on the data bus, i.e., from all 0s to all 1s, and vice versa.
D

AD5300BRTZ-500RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC RR VTG Output 8-Bit IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union