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ISL24201IRTZ-T13

P1-P3P4-P6P7-P9P10-P12
ISL24201
4
FN7586.1
December 9, 2010
Absolute Maximum Ratings Thermal Information
Supply Voltage
A
VDD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DD
+0.3V
Output Voltage with respect to Ground
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
VDD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . .1.5kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical) θ
JA
(°C/W) θ
JC
(°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 53 11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
A
VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: V
DD
= 3.3V, A
VDD
= 18V, R
SET
= 5kΩ, R
1
= 10kΩ, R
2
= 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at T
A
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
DC CHARACTERISTICS
V
DD
V
DD
Supply Range - Operating 2.25 3.6 V
A
VDD
A
VDD
Supply Range Supporting EEPROM Programming 10.8 19 V
A
VDD
A
VDD
Supply Range for Wide-Supply Operation
(not supporting EEPROM Programming)
4.5 19 V
I
DD
V
DD
Supply Current WP = SCL = SDA = V
DD
37 65 µA
I
AVDD
A
VDD
Supply Current WP = SCL = SDA = V
DD
24 38 µA
OUT CHARACTERISTICS
SET
ZSE
SET Zero-Scale Error ±3 LSB
SET
FSE
SET Full-Scale Error ±8 LSB
V
OUT
OUT Voltage Range I
OUT
< 0.5mA V
SET
+ 0.4 A
VDD
V
SET
VD
SET Voltage Drift 7 μV/°C
I
OUT
Maximum OUT Sink Current 4mA
INL Integral Non-Linearity ±2 LSB
DNL Differential Non-Linearity ±1 LSB
I
2
C INPUTS AND OUTPUT
I
2
CV
IH
SDA, SCL Logic 1 Input Voltage 1.44 V
I
2
CV
IL
SDA, SCL Logic 0 Input Voltage 0.55 V
I
2
C
H
SDA, SCL Hysteresis 260 mV
I
L
Input Leakage Current of SDA, SCL ±1 µA
VOL
S
SDA Output Logic Low I = -3mA 0.4 V
V
IH
WP Input Logic High 0.7V
DD
V
V
IL
WP Input Logic Low 0.3V
DD
V
V
WPH
WP Input Hysteresis 260 mV
IL
WPN
WP Input Leakage Current -0.20 -0.5 -1 µA
ISL24201
5
FN7586.1
December 9, 2010
Application Information
The ISL24201 provides the ability to adjust the V
COM
voltage
during production test and alignment, under digital control, to
minimize the flicker of an LCD panel. A digitally controlled
potentiometer (DCP), with 256 steps of resolution, adjusts the sink
current of the OUT pin. Figure 3 shows the V
COM
adjustment using
a mechanical potentiometer circuit and the equivalent circuit
replacement with the ISL24201.
The output is connected to an external voltage divider, as shown in
Figure 3, so that the ISL24201 will have the ability to reduce the
voltage on the output by increasing the OUT pin sink current. The
amount of current sunk is controlled by the I
2
C serial interface.
I
2
C TIMING
f
CLK
I
2
C Clock Frequency 400 kHz
t
SCH
I
2
C Clock High Time 0.6 µs
t
SCL
I
2
C Clock Low Time 1.3 µs
t
DSP
I
2
C Spike Rejection Filter Pulse Width 050ns
t
SDS
I
2
C Data Set Up Time 250 ns
t
SDH
I
2
C Data Hold Time 250 ns
t
BUF
I
2
C Time Between Stop and Start 200 µs
t
STS
I
2
C Repeated Start Condition Set-up 0.6 µs
t
STH
I
2
C Repeated Start Condition Hold 0.6 µs
t
SPS
I
2
C Stop Condition Set-up 0.6 µs
C
SDA
SDA Pin Capacitance 10 pF
C
S
SCL Pin Capacitance 10 pF
t
W
EEPROM Write Cycle Time 100 ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications Test Conditions: V
DD
= 3.3V, A
VDD
= 18V, R
SET
= 5kΩ, R
1
= 10kΩ, R
2
= 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at T
A
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
OUT
SET
ISL24201
or
ISL24202
R
1
R
2
A
VDD
A
VDD
V
COM
I
OUT
V
DD
R
SET
R
A
R
C
A
VDD
V
COM
R
B
R
1
= R
A
R
2
= R
B
+R
C
R
SET
= R
A
R
B
+ R
A
R
C
20R
B
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
ISL24201
6
FN7586.1
December 9, 2010
DCP (Digitally Controlled Potentiometer)
Figure 4 shows the relationship between the register value and
the resistor string of the DCP. Note that the register value of zero
actually selects the first step of the resistor string. The output
voltage of the DCP is given by Equation 1:
Output Current Sink
Figure 5 shows the schematic of the OUT pin current sink. The
circuit made up of amplifier A1, transistor Q1, and resistor R
SET
forms a voltage controlled current source.
The external R
SET
resistor sets the full-scale sink current that
determines the lowest output voltage of the external voltage divider
R
1
and R
2
. I
OUT
is calculated as shown by Equation 2:
The maximum value of I
OUT
can be calculated by substituting the
maximum register value of 255 into Equation 2, resulting in
Equation 3:
Equation 2 can also be used to calculate the unit sink current
step size by removing the Register Value term from it as shown in
Equation 4.
The voltage difference between the OUT pin and SET pin, which are
also the drain and source of the output transistor, should be greater
than the minimum saturation voltage for the I
OUT(MAX)
being used.
This will keep the output transistor in its saturation region to
maintain linear operation over the full range of register values.
Figure 6 shows I
DS
vs V
DS
for transistor Q1. The line labeled
"Minimum Saturation Voltage" is the minimum voltage that should
be maintained across the drain and source of Q1. To find the
minimum saturation voltage for a specific condition, locate the
voltage at the intersection of the I
OUT(MAX)
value from Equation 3
and the line labeled "Minimum Saturation Voltage".
V
DCP
RegisterValue 1+
256
---------------------------------------------------
⎝⎠
⎛⎞
A
VDD
20
--------------
⎝⎠
⎛⎞
=
(EQ. 1)
A
VDD
19R
R
0
1
2
255
254
253
252
251
REGISTER
VALUE
A
VDD
20
V
DCP
FIGURE 4. SIMPLIFIED SCHEMATIC OF DIGITAL CONTROL
POTENTIOMETER (DCP)
A
VDD
R
SET
V
DCP
SET
OUT
A
VDD
I
OUT
R
1
R
2
V
SAT
V
SET
= (I
OUT
)*(R
SET
) = V
DCP
Q1
A1
V
OUT
FIGURE 5. CURRENT SINK CIRCUIT
I
OUT
V
DCP
R
SET
-------------
RegisterValue 1+
256
---------------------------------------------------
⎝⎠
⎛⎞
A
VDD
20
--------------
⎝⎠
⎛⎞
1
R
SET
-------------
⎝⎠
⎛⎞
==
(EQ. 2)
I
OUT
MAX()
A
VDD
20R
SET
--------------------
=
(EQ. 3)
I
STEP
A
VDD
256()20()R
SET
()
----------------------------------------------
=
(EQ. 4)
FIGURE 6. I
DS
vs V
DS
FOR THE ISL24201 OUTPUT TRANSISTOR
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
012345678910
VDS (V)
SATURATION REGION
IDS (mA)
MINIMUM SATURATION
VOLTAGE
P1-P3P4-P6P7-P9P10-P12

ISL24201IRTZ-T13

Mfr. #:
Buy ISL24201IRTZ-T13
Manufacturer:
Renesas / Intersil
Description:
LCD Gamma Buffers ISL24201IRTZ VCOM CLBTR W/AN I2C
Lifecycle:
New from this manufacturer.
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