ISL24201IRTZ-T13

ISL24201
7
FN7586.1
December 9, 2010
The maximum voltage on the SET pin is A
VDD
/20 and is added to
the minimum voltage difference between the V
OUT
and SET pins to
calculate the minimum V
OUT
voltage, as shown in Equation 5.
Output Voltage
The output voltage, V
OUT
, of the OUT pin can be calculated from
Equation 6:
While Equation 6 can be used to calculate the output voltage, it
does not help select the values of R
1
, R
2
and R
SET
to obtain a
specific range of V
COM
voltages.
Output Voltage Span Calculation
The span of the output voltage is typically centered around the
nominal V
COM
voltage value, which is typically near half of the
A
VDD
voltage. The high V
COM
voltage occurs with the register
value of zero, while the low V
COM
voltage occurs with the register
value of 255. Figure 7 shows the definition of several terms used
later in the text.
There are three variables that control the V
COM
calibrator’s
operating point; the span of the V
COM
voltage, the maximum
current sink and the source impedance of the resistive divider.
Figure 8 shows a range of operating points for these three variables
and a quick way to estimate a specific operating point. The X-axis is
the span of the V
COM
voltage (High V
COM
Voltage - Low V
COM
Voltage), and the Y-axis is the maximum sink current set by R
SET
.
The individual plots of each R
TH
show the V
COM
span plotted against
the maximum OUT sink current given that value of source
impedance of the voltage divider. R
TH
is the Thevenin equivalent
resistance of the voltage divider R
1
and R
2
, which is the resistance
of the parallel combination of R
1
and R
2
, as shown in Equation 7.
The span of the V
COM
voltage is shown by Equation 8.
To make a final selection of the resistor values for R
1
and R
2
, The
supply voltage A
VDD
and the value of R
SET
are specified. The
calculations for R
1
and R
2
are shown in Equations 9 and 10:
The R
1
and R
2
calculations are based on the span of the V
COM
voltage being centered at half the A
VDD
voltage.
As an example, A
VDD
= 15V, the maximum value for I
SET
is
selected to be 100µA and the required span is 2V. Using Figure 8
as a guide, the V
COM
maximum is equal to 8.5V and the V
COM
minimum is equal to 6.5V. Rearranging equation and calculation
the value of R
SET
:
Calculating the value of R
1
is shown in Equation 12.
Calculating the value of R
2
is shown in Equation 13.
V
OUT
MIN()
A
VDD
20
--------------
MinimumSaturationVoltage+
(EQ. 5
)
V
OUT
A
VDD
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
RegisterValue 1+
256
---------------------------------------------------
R
1
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 6)
GND
A
VDD
NOMINAL V
COM
VOLTAGE
HIGH V
COM
VOLTAGE
LOW V
COM
VOLTAGE
SPAN
FIGURE 7. VOLTAGE LEVELS FOR V
COM
R
TH
R
1
R
2
R
1
R
2
+
--------------------
=
(EQ. 7
)
V
COM
SPAN I
SET
R
TH
()=
(EQ. 8
)
FIGURE 8. GRAPH of V
COM
SPAN vs MAXIMUM OUTCURRENT
AND R
TH
0.6
0.5
0.4
0.3
0.2
0.1
0
0123456
V
COM
SPAN (V)
OUT PIN MAXIMUM CURRENT (mA)
R
T
H
=
1
0
k
Ω
R
T
H
=
2
5
k
Ω
R
T
H
=
5
0
k
Ω
R
T
H
=
1
0
0
k
Ω
R
1
40R
SET
SPAN()
A
VDD
SPAN+
----------------------------------------- -
=
(EQ. 9
)
R
2
40R
SET
SPAN()
A
VDD
SPAN
----------------------------------------- -
=
(EQ. 10)
R
SET
A
VDD
20I
OUT
MAX()
-------------------------------------
15
20 0.000100()
--------------------------------------
7500Ω== =
(EQ. 11)
R
1
40 7500()2()
15 2+
-----------------------------------
39.29kΩ==
(EQ. 12)
R
2
40 7500()2()
15 2
-----------------------------------
46.15kΩ==
(EQ. 13)
ISL24201
8
FN7586.1
December 9, 2010
Table 1 shows the calculated results of the V
COM
voltage with
these values.
Figure 6 is used to find the minimum saturation voltage for an
I
OUT
maximum of 100µA, which is about 0.3V. The minimum
V
OUT
is 6.5V, which also meets the minimum V
OUT
- V
SET
requirements specified in Equation 14:
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, there is a
leakage current flowing into the pin in addition to the I
SET
current. Figure 9 shows the I
SET
current and the OUT pin current
for OUT pin voltage up to 19V. In applications where the voltage
on the OUT pin will be greater than 10V, the actual output voltage
will be lower than the voltage calculated by Equation 6. The
graph in Figure 9 was measured with R
SET
= 4.99kΩ.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 10. When applying power, V
DD
should be applied before or
at the same time as A
VDD
. The minimum time for t
VS
is 0µs.
When removing power, the sequence of V
DD
and A
VDD
is not
important.
Do not remove V
DD
or A
VDD
within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, A
VDD
must be 10.8V. If programming
is not required, the ISL24201 will operate over an A
VDD
range of
4.5V to 19V.
During EEPROM programming, I
DD
and I
AVDD
will temporarily be
higher than their quiescent currents. Figure 11 shows a typical
I
DD
and I
AVDD
current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 12. The algorithm
allows up to 4 erase cycles and 4 programming cycles, however
typical parts only require 1 cycle of each, sometimes 2 when
A
VDD
is near the minimum 10.8V limit.
TABLE 1. EXAMPLE V
OUT
vs REGISTER VALUE
REGISTER VALUE V
OUT
(V)
08.49
20 8.34
40 8.18
60 8.02
80 7.87
100 7.71
120 7.55
127 7.50
140 7.40
160 7.24
180 7.09
200 6.93
220 6.77
240 6.62
255 6.50
V
OUT
MIN 6.5V
15V
20
----------
> 0.3V+ 1.05V==
(EQ. 14)
0.000
0.050
0.100
0.150
0.200
0.250
0.300
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
OUT Pin Voltage (V)
OUT and SET Pin Current vs. OUT Pin Voltage
Register = 255
OUT Pin Current
SET Pin Current
Current (mA)
FIGURE 9. OUT PIN LEAKAGE CURRENT
V
DD
A
VDD
t
VS
FIGURE 10. POWER SUPPLY SEQUENCE
ISL24201
9
FN7586.1
December 9, 2010
ISL24201 Programming
The ISL24201 accepts I
2
C bus address and data when the WP
pin is at or above V
IH
(>0.7V
DD
). The ISL24201 ignores the I
2
C
bus when the WP
pin is at or below V
IL
(<0.3V
DD
). Figure 13
shows the serial data format for writing the register and
programming the EEPROM. Figure 14 shows the serial data
format for reading the DAC register. Table 2 shows the truth table
for reading and writing the device.
Programming the EEPROM memory transfers the current DAC
register value to the EEPROM and occurs when the control bits
select the programming mode and the A
VDD
voltage is >10.8V.
After the EEPROM programming cycle is started, the WP pin can
be returned to logic low while the while it completes, which takes
a maximum of 100ms.
The ISL24201 uses a 6 bit I
2
C address, which is “100111xx”. The
complete read and write protocol is shown in Figures 13 and 14.
I
2
C Bus Signals
The ISL24201 uses fixed voltages for its I
2
C thresholds, rather
than the percentage of V
DD
described in the I
2
C specification
(see Table 3). This should not cause a problem in most systems,
but the I
2
C logic levels in a specific design should be checked to
ensure they are compatible with the ISL24201.
VDD
Programming
Current
~1ms
IAVDD
Programming
Current
I
P
100ms
Max
2.7mA
200µA
50µA
90µA
25µA
FIGURE 11. I
DD
AND I
AVDD
CURRENT PROFILE DURING EEPROM
PROGRAMMING
FIGURE 12. EEPROM PROGRAMMING FLOWCHART
Erase Pulse
Start EEPROM
Programming
Are EEPROM
Cells Erased?
No
Yes
W rite Pulse
Are
EEPROM Cells
Programmed?
EEPROM
Programming
Complete
No
Yes
TABLE 2. ISL24201 READ AND WRITE CONTROL
WP
PIN I
2
C BITS FUNCTION
R/W
PROGRAM
0 1 X Read Register.
0 0 1 Will acknowledge I
2
C
transactions. Will not write to
register
0 0 0 Will acknowledge I
2
C
transactions. Will not write to
EEPROM.
1 1 X Read DAC Register
101Write DAC Register
100 Program EEPROM
TABLE 3. ISL24201 I
2
C BUS LOGIC LEVELS
SYMBOL ISL24201 I
2
C STANDARD
I
2
CV
IL
0.55V 0.3*V
DD
I
2
CV
IH
1.44V 0.7*V
DD

ISL24201IRTZ-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LCD Gamma Buffers ISL24201IRTZ VCOM CLBTR W/AN I2C
Lifecycle:
New from this manufacturer.
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