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TIMING AND READOUT OF THE IMAGE SENSOR
The timing of the sensor consists of two parts. The first
part is related with the integration time and the control of the
pixel. The second part is related to the readout of the image
sensor. Integration and readout can be in parallel. In this
case, the integration time of frame I is ongoing during
readout of frame I-1. Figure 14 shows this parallel timing
structure.
The readout of every frame starts with a Frame Overhead
Time (FOT) during which the analog value on the pixel
diode is transferred to the pixel memory element. After this
FOT, the sensor is read out line per line. The readout of every
line starts with a Row Overhead Time (ROT) during which
the pixel value is put on the column lines. Then the pixels are
selected in groups of 4. So in total 160 kernels of 4 pixels are
read out. The internal timing is generated by the sequencer.
The sequencer can operate in 2 modes: master mode and
slave mode. In master mode all the internal timing is
controlled by the sequencer, based on the SPI settings. In
slave mode the integration timing is directly controlled over
three pins, the readout timing is still controlled by the
sequencer. The selection between master and slave mode is
done by the MASTERMODE register of the SPI. The
sequencer is clocked on the core clock; this is the same clock
as the ADCs. The core clock is the input clock divided by 4.
Figure 14. Global Readout Timing
Readout Lines
Integration frame I+1 Integration frame I+2
Readout frame I Readout frame I+1
FOT L1
L2 L480
...
ROT K1
K2 K160
...
Readout Pixels
Integration Timing in Mastermode
In mastermode the integration time, the dual slope (DS)
integration time, and triple slope (TS) integration time are
set by the SPI settings. Figure 15 shows the integration
timing and the relationship with the SPI registers. The
timing concerning integration is expressed in number of
lines read out. The timing is controlled by four SPI registers
which need to be uploaded with the desired number of lines.
This number is then compared with the line counter that
keeps track of the number of lines that is read out.
RES1_LENGTH <11:0>: The number of lines read out
(minus 1) after which the pixel reset drops and the
integration starts.
RES2_TIMER <11:0>: The number of lines read out
(minus 1) after which the dual slope reset pulse is given. The
length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
RES3_TIMER < 11:0>: The number of lines read out
(minus 1) after which the triple slope reset pulse is given.
The length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
FT_TIMER <11:0>: The number of lines read out (minus
1) after which the Frame Transfer (FT) and the FOT starts.
The length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
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Figure 15. Integration Timing in Master Mode
RESET_N
RESET
PIXEL
1
Res1_length Res2_timer Res3_timer FT_timer
1FOT
Res1_length
PIXEL
SAMPLE
# LINES
READOUT
The line counter starts with the value 1 immediately after
the rising edge of RESET_N and after the end of the FOT.
This means that the four integration timing registers must be
uploaded with the desired number of lines plus one.
In subsampling mode, the line counter increases with
steps of two. In this mode, the counter starts with the value
‘2’ immediately with the rising edge of RESET_N. This
means that for correct operation, the four integration timing
registers can only be uploaded with an even number of lines
if subsampling is enabled.
The length of the integration time, the DS integration time
and the TS integration time are indicated by 3 output pins:
INT_TIME_1, INT_TIME_2 and INT_TIME_3. These
outputs are high during the actual integration time. This is
from the falling edge of the corresponding reset pulse to the
falling edge of the internal pixel sample. Figure 16 illustrates
this. The internal pixel sample rises at the moment defined
by FT_TIMER (see Figure 15) and the length of the pulse is
4*(12*(GRAN<1:0>+1)+2).
Figure 16. INT_TIME Timing
RESET_N
RESET
RESET
DS
RESET
TS
INT_TIME1
INT_TIME2
INT_TIME3
(internal)
Total Integration Time
DS Integration Time
TS Integration
Time
Frame
Transfer
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Readout Time Smaller Than or Equal to Integration Time
In this situation the RES_LENGTH register can be
uploaded with the smallest possible value, this is the value
’2’. The frame rate is determined by the integration time.
The readout time is equal to the integration time, the
FT_TIMER register is uploaded with a value equal to the
window size to readout plus one. In case the readout time is
smaller than the integration time the FT_TIMER register is
uploaded with a value bigger than the window size.
Figure 17 shows this principle. While the sensor is being
readout the FRAME_VALID signal goes high to indicate the
time needed to read out the sensor.
When windowing in Y direction is desired in this mode
(longer integration time than read out time) the following
parameters should be set: The integration time is set by the
FT_TIMER register. The actual windowing in Y is achieved
when the surrounding system discards the lines which are
not desired for the selected window.
Figure 17. Readout Time Smaller than Integration Time
FRAME_VALID
Total Integration Time
FT_TIMER
FOT FOT
Readout
PIXEL
RESET
Readout Time Larger Than Integration Time
In case the readout time is larger than then integration
time, the RES_LENGTH register needs to be uploaded with
a value larger than two to compensate for the larger readout
time. The FT_TIMER register must be set to the desired
window size (in Y). Only the RES_LENGTH register needs
to be changed during operation. Figure 18 shows this
example.
Figure 18. Readout Time Larger than Integration Time
FRAME_ VALID
Integration Time
FT_TIMER
FOT FOT
Readout
PIXEL
RESET
Integration Timing in Slave Mode
In slave mode, the registers RES_LENGTH, DS_TIMER,
TS_TIMER, and FT_TIMER are ignored. The integration
timing is now controlled by the pins INT_TIME_1,
INT_TIME_2 and INT_TIME_3, which are now active low
input pins.
The relationship between the input pins and the
integration timing is illustrated in Figure 19. The pixel is
reset as soon as IN_TIME_1 is low (active) and
INT_TIME_2 and INT_TIME_3 are high. The integration
starts when INT_TIME_1 becomes high again and during
this integration additional (lower) reset can be given by
activating INT_TIME_2 and INT_TIME_3 separately. At
the end of the desired integration time the frame transfer
starts by making all 3 INT_TIME pins active low
simultaneously. There is always a small delay between the
applied external signals and the actual internally generated
pulses. These delays are also shown in Figure 19.
In case non destructive readout is used, the pulses on the
input pins still need to be given. By setting the NDR bit to
“1” the internal pixel reset pulses are suppressed but the
external pulses are still needed to have the correct timing of
the frame transfer.

NOIL1SM0300A-WWC

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Manufacturer:
ON Semiconductor
Description:
Image Sensors VITA25KCOLORMLPGA355
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