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NOIL1SM0300A-WWC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NOIL1SM0300A
www.onsemi.com
19
Figure 19. Integration Timing in Slave Mode
INT_TIME_1
INT_TIME_2
DS RESET
(internal)
TS RESET
(internal)
PIXEL SAMPLE
(internal)
Total Integration Time
DS Integration Time
TS Integration
Time
SPI
RESET_N
INT_TIME_3
FOT FOT
Simultanious
min 12 clk
periods
min 12 clk
periods
RESET
(internal)
Readout Timing
The sensor is readout row by row. The LINE_VALID
signal shows when valid data of a row is at the outputs.
FRAME_VALID shows which LINE_VALIDs are valid.
LINE_VALIDs when FRAME_VALID is low, must be
discarded. Figure 20 and Figure 21 illustrate this.
NOTE: The FRAME_VALID signal automatically goes
low after 480 LINE_VALID pulses in
mastermode.
Figure 20. LINE_VALID Timing
12.5ns
Valid ValidValid Valid Valid Valid
CLK
Invalid
DATA
<9:0>
LINE_VALID
Invalid Invalid
Figure 21. FRAME_VALID Timing
FRAME_VALID
LINE_VALID
NOIL1SM0300A
www.onsemi.com
20
The data at the output of the sensor is clocked on the rising
edge of CLK. There is a delay of 3.2 ns between the rising
edge of CLK and a change in DATA<9:0>. After this delay
DATA<9:0> needs 6 ns to become stable within 10% of
VDDD. This means that DATA<9:0> is stable for a time
equal to the clock period minus 6 ns. Figure 22 illustrates
this.
NOTE: In slave mode, line valids that occur beyond the
desired image window should be discarded by
the user’s image data acquisition system
Figure 22. DATA<9.0> Valid Timing
DATA <9:0>
INVALID
CLK
VALID INVALID  INVALID
VALID
LINE_VALID 4ns
3.2 + 6ns
Clk period - 6ns
3.2ns
6ns
Readout Timing in Slave Mode
The start pointer of the window to readout is determined
by the START_X and START_Y registers (as by readout in
master mode). The size of the window in x-direction is also
determined by the NB_OF_PIX register. The length of the
window in y-direction is determined by the externally
applied integration timing. The sensor does not know the
desired y-size to readout. It therefore reads out all lines
starting from START_Y. The readout of lines continues until
the user decides to start the FOT.
Even when the line pointer wants to address non existing
rows (row 481 and higher), the sequencer continues to run
in normal readout mode. This means that FRAME_VALID
remains high and LINE_VALID is toggled as if normal lines
are readout.
The controller should take care of this and ignore the
LINE_VALIDs that correspond with non existing lines and
LINE_VALIDs that correspond with lines that are not inside
the desired readout window.
The length of the FOT and ROT is still controlled by the
GRAN register as described in this data sheet.
Readout time longer than integration time
The sensor should be timed according to the formulas and
diagram here:
1. INT_TIME_1 should be brought high at time
(read_t - int_t) and preferably immediately after
the falling edge of LINE_VALID.
2. At time read_t all INT_TIME_x should
simultaneous go low to start the FOT. This is
immediately after the falling edge of the last
LINE_VALID of the desired readout window.
FOT Readout FOT
INT_TIME1
Reset Integration
Readout time shorter than integration time
The sensor should be timed according to the formulas and
diagram here:
1. INT_TIME_1 should be brought high after a
minimum 2 ms reset time and preferably
immediately after the falling edge of the first
LINE_VALID.
2. At time read_t after the last valid LINE_VALID of
the desired window size, all other LINE_VALIDs
should be ignored.
3. After the desired integration length all
INT_TIME_x should simultaneous go low to start
the FOT.
FOT Readout FOT
INT_TIME1
Reset Integration
Dummy
LINE_VALIDs
NOIL1SM0300A
www.onsemi.com
21
Startup Timing
On startup, VDDD should rise together with or before the
other supplies. The rise of VDDD should be limited to
1V/100 ms to avoid activation of the on chip ESD protection
circuitry.
During the rise of VDDD an on chip POR_N signal is
generated that resets the SPI registers to its default setting.
After VDDD is stable the SPI settings can be uploaded to
configure the sensor for future readout and light integration.
When powering on the VDDD supply, the RESET_N pin
should be kept low to reset the on chip sequencer and
addressing logic. The RESET_N pin must remain low until
all initial SPI settings are uploaded. RESET_N pin must
remain low for at least 500 ns after ALL supplies are stable.
The rising edge of RESET_N starts the on chip clock
division. The second rising edge of CLK after the rising edge
of RESET_N, triggers the rising edge of the core clock.
Some SPI settings can be uploaded after the core clock has
started.
Figure 23. Startup Timing
POWER ON VDDD STABLE
SPI upload
Min 500ns
SPI upload if requiredINVALIDINVALIDSPI upload
VDDD power
supply
Core clock
(internal)
System clock
(external)
RESET_N
POR_N
(internal)
Sequencer Reset Timing
By bringing RESET_N low for at least 50 ns, the on chip
sequencer is reset to its initial state. The internal clock
division is restarted. The second rising edge of CLK after the
rising edge of RESET_N the internal clock is restarted. The
SPI settings are not affected by RESET_N. If needed the SPI
settings can be changed during a low level of RESET_N.
Figure 24. Sequencer Reset Timing
System
(internal)
Normal operation Normal operationINVALID
Min 50 ns
clock
(external)
RESET_N
Core clock
(internal)
Sync_Y
(internal)
Clock_Y
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NOIL1SM0300A-WWC

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Buy NOIL1SM0300A-WWC
Manufacturer:
ON Semiconductor
Description:
Image Sensors VITA25KCOLORMLPGA355
Lifecycle:
New from this manufacturer.
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