PHK18NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 December 2010 2 of 11
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1Ssource
SOT96-1 (SO8)
2Ssource
3Ssource
4 G gate
5 D drain
6 D drain
7 D drain
8 D drain
4
5
1
8
S
D
G
bb076
Table 3. Ordering information
Type number Package
Name Description Version
PHK18NQ03LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 150 °C - 30 V
V
DGR
drain-gate voltage T
j
≥ 25 °C; T
j
≤ 150 °C; R
GS
=20kΩ -30V
V
GS
gate-source voltage -20 20 V
I
D
drain current T
sp
=100°C; V
GS
= 10 V; see Figure 1 - 12.1 A
T
sp
=25°C; V
GS
=10V; see Figure 1 - 20.3 A
I
DM
peak drain current T
sp
= 25 °C; pulsed; t
p
≤ 10 µs - 80 A
P
tot
total power dissipation T
sp
=25°C; see Figure 2 -6.25W
T
stg
storage temperature -55 150 °C
T
j
junction temperature -55 150 °C
Source-drain diode
I
S
source current T
sp
=25°C - 5.2 A
I
SM
peak source current T
sp
= 25 °C; pulsed; t
p
≤ 10 µs - 20.8 A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
V
GS
=10V; T
j(init)
=25°C; I
D
= 31.5 A;
V
sup
≤ 25 V; unclamped; t
p
= 0.07 ms;
R
GS
=50Ω
-50mJ
