PHK18NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 December 2010 5 of 11
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
drain-source breakdown voltage I
D
= 250 µA; V
GS
=0V; T
j
= -55 °C 27 - - V
I
D
= 250 µA; V
GS
=0V; T
j
=25°C 30--V
V
GS(th)
gate-source threshold voltage I
D
=1mA; V
DS
=V
GS
; T
j
=150°C;
see Figure 3; see Figure 4
0.8--V
I
D
=1mA; V
DS
=V
GS
; T
j
=25°C;
see Figure 3
; see Figure 4
1.3 1.7 2.15 V
I
D
=1mA; V
DS
=V
GS
; T
j
=-55°C;
see Figure 3; see Figure 4
--2.6V
I
DSS
drain leakage current V
DS
=30V; V
GS
=0V; T
j
=25°C --1µA
I
GSS
gate leakage current V
GS
=16V; V
DS
=0V; T
j
= 25 °C - - 100 nA
V
GS
=-16V; V
DS
=0V; T
j
= 25 °C - - 100 nA
R
DSon
drain-source on-state resistance V
GS
=10V; I
D
=25A; T
j
=150°C;
see Figure 5
- 12.1 15.1 mΩ
V
GS
=4.5V; I
D
=25A; T
j
=25°C;
see Figure 5
- 10.1 12.5 mΩ
V
GS
=10V; I
D
=25A; T
j
=25°C;
see Figure 5
-7.18.9mΩ
I
DSS
drain leakage current V
DS
=30V; V
GS
=0V; T
j
= 150 °C - - 100 µA
R
G
gate resistance f = 1 MHz - 1.6 - Ω
Dynamic characteristics
Q
G(tot)
total gate charge I
D
=15A; V
DS
=12V; V
GS
=4.5V;
see Figure 6
- 10.6 - nC
Q
GS
gate-source charge - 4.85 - nC
Q
GS1
pre-threshold gate-source charge - 2.4 - nC
Q
GS2
post-threshold gate-source
charge
-2.45-nC
Q
GD
gate-drain charge - 2.5 - nC
V
GS(pl)
gate-source plateau voltage I
D
=15A; V
DS
=12V; see Figure 6 -3-V
C
iss
input capacitance V
DS
=12V; V
GS
=0V; f=1MHz;
T
j
=25°C
- 1380 - pF
V
DS
=0V; V
GS
= 0 V; f = 1 MHz;
T
j
=25°C
- 1590 - pF
C
oss
output capacitance V
DS
=12V; V
GS
=0V; f=1MHz;
T
j
=25°C
- 290 - pF
C
rss
reverse transfer capacitance - 135 - pF
t
d(on)
turn-on delay time V
DS
=12V; R
L
=0.8Ω; V
GS
=4.5V;
R
G(ext)
=5.6Ω
-19-ns
t
r
rise time - 22 - ns
t
d(off)
turn-off delay time - 19 - ns
t
f
fall time - 11 - ns
