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DS1673S-3+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DS1673
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POWER-UP/POWER-DOWN CONSIDERATIONS
When V
CC
is applied to the DS1673 and reaches a level greater than V
CCTP
(power-fail trip point), the
device becomes fully accessible after t
RPU
(250ms typical). Before t
RPU
elapses, all inputs are disabled.
When V
CC
drops below V
CCSW
, the device is switched over to the V
BAT
supply.
During power-up, when V
CC
returns to an in-tolerance condition, the RST pin is kept in the active state
for 250ms (typical) to allow the power supply and microprocessor to stabilize.
ADDRESS/COMMAND BYTE
The command byte for the DS1673 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the address of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a one. The address map for the DS1673 is
shown in Figure 3.
ADDRESS/COMMAND BYTE Figure 2
DS1673
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DS1673 ADDRESS MAP Figure 3
CLOCK, CALENDAR, AND ALARM
The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that
some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note that
registers 0Fh to 7Fh are reserved. These registers will always read 0 regardless of how they are written.
The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format.
The DS1673 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or
24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the
AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours).
The DS1673 also contains a time of day alarm. The alarm registers are located in registers 07h to 0Ah.
Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an
alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm
will occur every second.
DS1673
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TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES HOURS DAYS
DESCRIPTION
1 1 1 1 Alarm once per second.
0 1 1 1 Alarm when seconds match.
0 0 1 1 Alarm when minutes and seconds match.
0 0 0 1 Alarm when hours, minutes and seconds match.
0 0 0 0 Alarm when day, hours, minutes and seconds
match.
SPECIAL PURPOSE REGISTERS
The DS1673 has two additional registers (control register and status register) that control the RTC and
interrupts.
CONTROL REGISTER
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC
WP AIS1 AIS0 0 0 0 AIE
EOSC
(Enable Oscillator). This bit, when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1673 is placed into a low-power standby mode with a current
drain of less than 200nA when in battery-backup mode. When the DS1673 is powered by V
CC
, the
oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only
when EOSC is a logic 0.
WP (Write Protect). Before any write operation to the RTC or any other registers, this bit must be logic
0. When high, the write protect bit prevents a write operation to any register.
AIS0-AIS1 (Analog Input Select). These 2 bits are used to determine the analog input for the analog-to-
digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.
AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)
bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the
INT signal.
ANALOG INPUT SELECTION Table 2
AIS1 AIS0 ANALOG INPUT
0 0 NONE
0 1 AIN0
1 0 AIN1
1 1 AIN2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

DS1673S-3+

Mfr. #:
Buy DS1673S-3+
Manufacturer:
Maxim Integrated
Description:
Real Time Clock Portable System Controller
Lifecycle:
New from this manufacturer.
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