DS1673S-3+ Datasheet DS1673S-3+, DS1673E-5+, DS1673E-3+ | P7-P9

DS1673

7 of 18

STATUS REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CU LOBAT 0 0 0 0 0 IRQF

CU (Conversion Update In Progress). When this bit is a 1, an update to the ADC Register (register

0Eh) will occur within 488s. When this bit is a 0, an update to the ADC Register will not occur for at

least 244s.

LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the

BAT

pin. When V

BAT

is greater than 2.5V, LOBAT is set to a logic 0. When V

BAT

is less than 2.3V,

LOBAT is set to a logic 1.

IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current

time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go

high. IRQF is cleared by reading or writing to any of the alarm registers.

POWER-UP DEFAULT STATES

These bits are set to a one upon initial power-up: EOSC, TD1 and TD0. These bits are cleared upon

initial power-up: WP, AIS1, and AIS0.

NONVOLATILE SRAM CONTROLLER

The DS1673 provides automatic backup and write protection for external SRAM. This function is

provided by gating the chip enable signals and by providing a constant power supply through the V

CCO

pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind. As

such, the DS1673 has the capability to provide access to the external SRAM in either byte-wide or word-

wide format. This capability is provided by the chip enable scheme. Three input signals and two output

signals are used for enabling the external SRAM(s) (see Figure 4). CEI (chip enable in), BHE (byte high

enable), and BLE (byte low enable) are used for enabling either one or two external SRAMs through the

CEOL (chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the function of

these pins.

The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a

back-up power supply in the absence of V

. When V

falls below V

, access to the external SRAM(s)

are prohibited by forcing

CEOL

and

CEOH

high regardless of the level of

CEI

, BLE , and BHE . Upon

power-up, access is prohibited until the end of t

RPU

EXTERNAL SRAM CHIP ENABLE Table 3

CEI

BHE BLE

CEOL CEOH

FUNCTION

0 0 0 0 0 Word transfer

0 0 1 1 0 Byte transfer in upper half of data bus (D15-D8)

0 1 0 0 1 Byte transfer in lower half of data bus (D7-D0)

0 1 1 1 1 External SRAMs disabled

1 X X 1 1 External SRAMs disabled

DS1673

8 of 18

EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1673 Figure 4

MICROPROCESSOR MONITOR

The DS1673 monitors three vital conditions for a microprocessor: power supply, software execution, and

external override.

First, a precision temperature-compensated reference and comparator circuit monitors the status of V

When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the

RST

pin to the active state, thus warning a processor-based system of impending power failure. When

returns to an in-tolerance condition upon power-up, the reset signal is kept in the active state for

250ms (typical) to allow the power supply and microprocessor to stabilize. Note, however, that if the

EOSC bit is set to a logic 1 (to disable the oscillator during battery-backup mode), the reset signal will be

kept in an active state for 250 ms plus the start-up time of the oscillator.

The second monitoring function is push-button reset control. The DS1673 provides for a pushbutton

switch to be connected to the RST output pin. When the DS1673 is not in a reset cycle, it continuously

monitors the

RST

signal for a low going edge. If an edge is detected, the DS1673 will debounce the

switch by pulling the RST line low. After the internal 250ms timer has expired, the DS1673 will continue

to monitor the RST line. If the line is still low, the DS1673 will continue to monitor the line looking for a

rising edge. Upon detecting release, the DS1673 will force the

RST

line low and hold it low for 250ms.

The third microprocessor monitoring function provided by the DS1673 is a watchdog timer. The

watchdog timer function forces

RST to the active state when the ST input is not stimulated within the

predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.

The time delay can be set to 250ms, 500ms, or 1000ms (see Figure 5). If TD0 and TD1 are both set to

zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set

time period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with

1000ms time delay. If a high-to-low transition occurs on the ST input pin prior to time-out, the watchdog

timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then the

RST

signal is driven to the active state for 250ms (typical). The

ST input can be derived from microprocessor

address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not time-

out, a high-to-low transition must occur at or less than the minimum period.

DS1673

9 of 18

WATCHDOG TIME-OUT CONTROL Figure 5

WATCHDOG REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 0 0 TD1 TD0

WATCHDOG REGISTER

TD1 TD0 WATCHDOG TIME-OUT

0 0 WATCHDOG DISABLED

0 1 250 ms

1 0 500 ms

1 1 1000 ms

ANALOG-TO-DIGITAL CONVERTER

The DS1673 provides a 3-channel, 8-bit analog-to-digital converter. The ADC reference voltage (2.55V

typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided

through the AIN0, AIN1, and AIN2 pins. The ADC is monotonic (no missing codes) and uses a

successive approximation technique to convert the analog signal into a digital code.

An A/D conversion is the process of assigning a digital code to an analog input voltage. This code

represents the input value as a fraction of the full-scale voltage (FSV) range. Thus, the FSV range is then

divided by the ADC into 256 codes (8 bits). The FSV range is bounded by an upper limit equal to the

reference voltage and the lower limit, which is ground. The DS1673 has a FSV of 2.55V (typical) that

provides a resolution of 10mV. An input voltage equal to the reference voltage converts to FFh while an

input voltage equal to ground converts to 00h. The relative linearity of the ADC is 0.5 LSB.

The A/D converter selects from one of three different analog inputs (AIN0–AIN2). The input that is

selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the

specific analog input that is selected by these 2 bits. Note also that the converter can be turned off by

these bits to reduce power. When the ADC is turned on by setting AIS0 and AIS1 to any value other than

0,0 the analog input voltage is converted and written to the ADC Register within 488s. An internal

analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every

10ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time.

The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can

be read. When this bit is a 1, an update to the ADC Register will occur within 488s maximum. However,

when this bit is 0 an update will not occur for at least 244s. The CU bit should be polled before reading

the ADC Register to insure that the contents are stable during a read cycle. Once a read cycle to the ADC

completed. It should also be mentioned that taking CS low will abort the read cycle and will allow the

ADC Register to be updated.

Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the

completion of that conversion.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

DS1673S-3+

Mfr. #:

Buy DS1673S-3+

Manufacturer:

Maxim Integrated

Description:

Real Time Clock Portable System Controller

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

DS1673S-3+

DS1673S-3+

Products related to this Datasheet