MAX4814E
DA1 select the connections of switch A to switch SW_
and inputs DB0 and DB1. Select the connections of
switch B to SW_. See Table 3a for the pin configuration
and Table 3b for a complete summary.
I
2
C Interface Method (Mode 1)
In mode 1, the switch connections are controlled
through the I
2
C interface. Inputs SDA and SCL program
registers R0 and R1. Register R0, bits [7 to 2], select
the connection of switch A and switch B to switch SW_
(see the
I
2
C Registers and Bit Descriptions
section).
The bits of register R1 transfer data to the output DO_.
The data on output DO_ is used to communicate with the
MAX3845. In mode 1, DA0/DO0 becomes output DO0,
DA1/DO1 becomes output DO1, DA2/DO2 becomes
output DO2, and DB0/DO3 becomes output DO3. DB1
and DB2 are high impedance. See Table 3a for the pin
configuration. See Table 4 for register R1 to DO_ output
mapping.
I
2
C Registers and Bit Descriptions
Two internal registers (RO and R1) program the
MAX4814E. Table 2 lists both registers, their address-
es, and power-up default states. Both registers are
read/write registers.
In register R0, bit BAEN is used as the enable for
switch A, and bit BBEN is used as the enable for switch
B. Writing 1 to bit BAEN enables switch A; and writing 0
to bit BAEN disables switch A. Writing 1 to bit BBEN
enables switch B, and writing 0 to bit BBEN disables
switch B. BASEL1 and BASEL0 select the connections
of switch A to switch SW_, while BBSEL1 and BBSEL0
select the connections of switch B to switch SW_, as
summarized in Table 6.
I
2
C Register R0 Two LSB Bits
The two LSBs are hard coded as 00. Register R0
ignores any value written to the two LSBs; anytime reg-
ister R0 is read the hard-coded values are returned.
Bank A Enable (BAEN) and Bank B Enable (BBEN) Bits
1 = Enable
0 = Disable
Bank A Select (BASEL1/BASEL0) and
Bank B Select (BBSEL1/BBSEL0) Bits
Bits BASEL1 and BASEL0 select the switch SW_ that
switch A is connected to. Bits BBSEL1 and BBSEL0
select the switch SW_ that switch B is connected to
(see Table 6).
Power-On Default States
When power is applied to the MAX4814E internal
power-on reset (POR), circuitry sets registers R0 and
R1 to their default states. Register R0 is set to all zeros,
or 00h, and register R1 is set to 10101010, or AAh, as
shown in Table 2.
Having all zeros in register R0 disables both banks A
and B; see Table 6 for register R0 to switch mapping.
Setting register R1 to AAh forces the outputs at DO_ to
be high impedance.
Note: The output, DO_ is used to communicate with the
MAX3845 when the MAX4814E is being used without its
companion. The MAX3845 and the MAX4814E use the
I
2
C interface (MODE = 1). All DO_ outputs need to be
connected through a 10kΩ resistor to GND.
DVI/HDMI 2:4 Low-Frequency Fanout Switch
10 ______________________________________________________________________________________
X = Hardwired code, not programmable by user.
Table 1. Mode Configuration
INPUT PIN
MODE
OPERATION
0 Puts the device in mode 0. The direct-control inputs DA_ and DB_ control the switches.
1
P uts the d evi ce i n m od e 1. The sw i tches ar e contr ol l ed b y the I
2
C i nter face. D O _ b ecom es an acti ve outp ut.
Inp uts D B1 and D B2 ar e hi g h i m p ed ance.
Table 2. I
2
C Register Map
BIT POWER-UP
REGISTER
76543210
ADDRESS
BINARY HEX
R0 BBEN
BBSE
L1
BBSEL0 BAEN BASEL1
BASE
L0
X X 0x00
0000
0000
00
R1
D O3
H i g h
Im p ed ance
DO3
Data
DO2
High
Im p ed ance
DO2
Data
DO1
High
Im p ed ance
DO1
Data
DO0
High
Im p ed ance
DO0
Data
0x01
1010
1010
AA
I
2
C Interface
The MAX4814E features an I
2
C interface using a
repeated start. The MAX4814E I
2
C interface refers to
the I
2
C bus specification (version 2.1, Jan 2000).
Device Address
The MAX4814E has selectable device addresses
through external inputs. The slave address consists of
four fixed bits (B7–B4, set to 0111) followed by three pin-
programmable bits (AD2–AD0), as shown on Table 7.
MAX4814E
DVI/HDMI 2:4 Low-Frequency Fanout Switch
______________________________________________________________________________________ 11
Table 3a. Input/Output Configurations for DA_, DB_, and DO_
PIN CONFIGURATION
MODE
DA0/DO0 DA1/DO1 DA2/DO2 DB0/DO3 DB1 DB2
0 DA0, Input DA1, Input DA2, Input DB0, Input DB1, Input DB2, Input
1 DO0, Output DO1, Output DO2, Output DO3, Output High Impedance High Impedance
Table 3b. Mode 0 Direct-Control Configurations
PIN CONNECTION
DB1 DB0 DA1 DA0
OPERATION
0 0 0 0 Connect A to SW0 B is high impedance
0 0 0 1 Connect A to SW1 Connect B to SW0
0 0 1 0 Connect A to SW2 Connect B to SW0
0 0 1 1 Connect A to SW3 Connect B to SW0
0 1 0 0 Connect A to SW0 Connect B to SW1
0 1 0 1 Connect A to SW1 B is high impedance
0 1 1 0 Connect A to SW2 Connect B to SW1
0 1 1 1 Connect A to SW3 Connect B to SW1
1 0 0 0 Connect A to SW0 Connect B to SW2
1 0 0 1 Connect A to SW1 Connect B to SW2
1 0 1 0 Connect A to SW2 B is high impedance
1 0 1 1 Connect A to SW3 Connect B to SW2
1 1 0 0 Connect A to SW0 Connect B to SW3
1 1 0 1 Connect A to SW1 Connect B to SW3
1 1 1 0 Connect A to SW2 Connect B to SW3
1 1 1 1 Connect A to SW3 B is high impedance
Note: When switch A and switch B are connected to the same SW_, switch A takes precedence and switch B is high impedance.
PIN CONNECTION
DA2
OPERATION
0 Bank A switches are disabled
1 Bank A switches are enabled. Switch A connections depend on the DA0 and DA1 inputs.
PIN CONNECTION
DB2
OPERATION
0 Bank B switches are disabled
1 Bank B switches are enabled. Switch B connections depend on the DB0 and DB1 inputs.
MAX4814E
For example: If AD0, AD1, and AD2 are hardwired to
ground, then the complete address is 0111000. The full
address is defined as the seven most significant bits
followed by the read/write bit. Set the read/write bit to 1
to configure the MAX4814E to read mode. Set the
read/write bit to 0 to configure the MAX4814E to write
mode. The address is the first byte of information sent
to the MAX4814E after the START condition.
.
Applications Information
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. Switch A, switch B, and switch SW_ are fur-
ther protected against static electricity. Maxim’s engi-
neers have developed state-of-the-art structures to
protect these pins against ESD up to ±6kV without
damage. The ESD structures withstand high ESD in
normal operation, and when the device is powered
down. ESD protection can be tested in various ways.
The ESD protection of switch A, switch B, and switch
SW_ are characterized for ±6kV (Human Body Model)
using the MIL-STD-883.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 7 shows the Human Body Model, and Figure 8
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest
that is then discharged into the test device through a
1.5kΩ resistor.
DVI/HDMI 2:4 Low-Frequency Fanout Switch
12 ______________________________________________________________________________________
Table 4. I
2
C Register R1 (0X01) to DO_ Mapping
PIN REGISTER R1 (0x01)
MODE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OUTPUT PIN
CONFIGURATION
1 0 0 DO0 0
1 0 1 DO0 1
1 1 X DO0 Hi-Z
1—0 0—DO10
1—0 1—DO11
1 1 X DO1 Hi-Z
1——0 0—DO20
1——0 1—DO21
1 1 X DO2 Hi-Z
100DO30
101DO31
1 1 X DO3 Hi-Z
Table 5. I
2
C Register R0 (0x00)
REGISTER R0 (0x00)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BBEN BBSEL1 BBSEL0 BAEN BASEL1 BASEL0 X X
X = Hardwired, not programmed by user.
X = Don’t care.

MAX4814EECB+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Video Switch ICs DVI/HDMI 2:4 Low-f Fanout Switch
Lifecycle:
New from this manufacturer.
Delivery:
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