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MAX4814EECB+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Power-Supply Biasing and Sequencing
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, since stresses beyond the listed ratings
can cause permanent damage to the device. Always
sequence V
DD
on first, followed by the switch inputs
and the logic inputs. Bypass at least one V
DD
input to
ground with a 0.1µF capacitor as close as possible to
the device. Use the smallest physical size possible for
optimal performance.
MAX4814E
DVI/HDMI 2:4 Low-Frequency Fanout Switch
______________________________________________________________________________________ 13
Table 6. Switch Selection Truth Table
DA_, DB_ INPUTS/REGISTER R0 BITS SWITCH A AND B TO SW_ CONNECTIONS
DB2/
BBEN
DB1/
BBSEL1
DB0/
BBSEL0
DA2/
BAEN
DA1/
BASEL1
DA0/
BASEL0
B TO
SW3
B TO
SW2
B TO
SW1
B TO
SW0
A TO
SW3
A TO
SW2
A TO
SW1
A TO
SW0
0 X X 0 X X ————————
0 X X 1 0 0 ——————— 1
0 X X 1 0 1 —————— 1 —
0 X X 1 1 0 ————— 1 ——
0 X X 1 1 1 ———— 1 ———
1 0 0 0 X X ——— 1 ————
1 0 0 1 0 0 ——— 0 ——— 1
10 010 1 ———1——1—
10 011 0 ———1—1——
1 0 0 1 1 1 ——— 1 1 ———
1 0 1 0 X X —— 1 —————
1 0 1 1 0 0 —— 1 ———— 1
1 0 1 1 0 1 —— 0 ——— 1 —
10 111 0 ——1——1——
1 0 1 1 1 1 —— 1 — 1 ———
1 1 0 0 X X — 1 ——————
1 1 0 1 0 0 — 1 ————— 1
1 1 0 1 0 1 — 1 ———— 1 —
11 011 0 —0———1——
1 1 0 1 1 1 — 1 —— 1 ———
1 1 1 0 X X 1 ———————
1 1 1 1 0 0 1 —————— 1
1 1 1 1 0 1 1 ————— 1 —
1 1 1 1 1 0 1 ———— 1 ——
1 1 1 1 1 1 0 ——— 1 ———
— = Denotes no connection.
1 = Denotes switch connection.
0 = Denotes switch B is high impedance.
X = Don’t care.
Table 7. MAX4814E Device Address
B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 1 AD2 AD1 AD0 R/W
Fixed User Selected —
MAX4814E
DVI/HDMI 2:4 Low-Frequency Fanout Switch
14 ______________________________________________________________________________________
SCL
SDA
REPEATED
START CONDITION
START
CONDITION
t
HD, STA
t
SU, STA
t
LOW
t
SU, DAT
t
HD, DAT
t
HIGH
t
r
t
f
Figure 4. 2-Wire Interface Timing Diagram
MAX4814E MAX3845
58
59
60
61
2223 211918 20
96
65
61
30
V
DD
SDA SCL
I
2
C CONTROL
SETS 3 LSBs OF I
2
C ADDRESS.
AS SHOWN ADDRESS = 0111 + LSB = 0111000.
THERE ARE 8 POSSIBLE I
2
C ADDRESSES.
BY HARDWIRING PINS 23, 22, AND 21 TO 1 OR 0 USER
CAN CHANGE ADDRESS.
SEE TABLE 4 FOR I
2
C REGISTERS.
MODE = 1: I
2
C CONTROL
3-STATE
CONTROL
Figure 5. Mode 1: I
2
C Control
MAX4814E
21
DA0
22
DA1
61
DB0
23
DA2
18
MODE = 0
62
DB1
63
DB2
SEE TABLE 3b FOR CONTROL FUNCTIONS.
MODE = 0: DIRECT CONTROL
Figure 6. Mode 0: Direct Control
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
C
s
100pF
R
C
1MΩ
R
D
1500Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 7. Human Body ESD Test Model
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
10%
0
0
AMPERES
Figure 8. Human Body Current Waveform
MAX4814E
DVI/HDMI 2:4 Low-Frequency Fanout Switch
______________________________________________________________________________________ 15
It is also recommended to bypass more than one V
DD
input. A good strategy is to bypass one V
DD
input with
a 0.1µF capacitor and at least a second V
DD
input with
a 1nF to 10nF capacitor (use a 0603 or smaller physical
size ceramic capacitor).
Chip Information
PROCESS: BiCMOS
Pin Configuration
58
59
60
61
62
54
55
56
57
63
38394041424344454647
DA1/DO1
A[0]
N.C.
TQFP
SW1[0]
SW1[1]
SW1[2]
SW1[3]
SW1[4]
V
DD
V
DD
SW2[0]
SW2[1]
52
53
49
50
51
SW2[2]
SW2[3]
SW2[4]
I.C.
GND
I.C.
A[2]
A[1]
A[4]
A[3]
V
DD
V
DD
B[1]
B[0]
B[3]
B[2]
I.C.
B[4]
GND
EFN
SW3[0]
SW3[1]
SW3[2]
SW3[3]
SW3[4]
GND
GND
AD2
AD1
3334353637
AD0
SCL
SDA
MODE
V
DD
DA0/DO0
GND
GND
SW0[0]
SW0[1]
V
DD
DB2
DB1
DB0/DO3
DA2/DO2
SW0[2]
SW0[3]
SW0[4]
EFN
48
V
DD
V
DD
64
GND
GND
23
22
21
20
19
27
26
25
24
18
29
28
32
31
30
17
11109876543216151413121
MAX4814E
TOP VIEW
*CONNECT EXPOSED PADDLE TO GND.
*EP
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

MAX4814EECB+

Mfr. #:
Buy MAX4814EECB+
Manufacturer:
Maxim Integrated
Description:
Video Switch ICs DVI/HDMI 2:4 Low-f Fanout Switch
Lifecycle:
New from this manufacturer.
Delivery:
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