5©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016
87946I-01 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= V
DDA
= V
DDB
= V
DDC
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDX
/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDX
/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at V
DDX
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDA
= V
DDB
= V
DDC
= 2.5V ± 5%, T
A
= -40°C to 85°C
For NOTES, please see Table 5A above.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
PD
Propagation Delay; NOTE 1 ƒ 250MHz 2.3 3.1 3.8 ns
tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at V
DDX
/2 30 ps
tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at V
DDX
/2 130 ps
tsk(w)
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge at V
DDX
/2 320 ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at V
DDX
/2 700 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
125MHz, 12kHz – 20MHz 0.19 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 400 950 ps
odc Output Duty Cycle 40 50 60 %
t
EN
Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns
t
DIS
Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
PD
Propagation Delay; NOTE 1 ƒ 250MHz 2.5 3.2 3.8 ns
tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at V
DDX
/2 35 ps
tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at V
DDX
/2 120 ps
tsk(w)
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge at V
DDX
/2 325 ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at V
DDX
/2 700 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
125MHz, 12kHz – 20MHz 0.19 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 350 800 ps
odc Output Duty Cycle 40 50 57 %
t
EN
Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns
t
DIS
Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns
