¤ Semiconductor Components Industries, LLC, 2006
November, 2006 ï Rev. 7
1 Publication Order Number:
MC10E416/D
MC10E416, MC100E416
5VECL Quint Differential
Line Receiver
Description
The MC10E416/100E416 is a 5-bit differential line receiving device.
The 2.0 GHz of bandwidth provided by the high frequency outputs
makes the device ideal for buffering of very high speed oscillators.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will
force the Q output of a gate in an open input condition to go to a LOW
state. Thus, inputs of unused gates can be left open and will not affect
the operation of the rest of the device. Note that the input clamp will
take affect only if both inputs fall 2.5 V below V
CC
.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
x Differential D and Q; V
BB
available
x 600 ps Max. Propagation Delay
x High Frequency Outputs
x 2 Stages of Gain
x PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
x NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= ï4.2 V to ï5.7 V
x Internal Input 50 kW Pulldown Resistors
x ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
x Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
x Moisture Sensitivity Level:
Pb = 1;
PbïFree = 3
For Additional Information, see Application Note AND8003/D
x Flammability Rating: UL 94 Vï0 @ 0.125 in,
Oxygen Index: 28 to 34
x Transistor Count = 201 devices
x PbïFree Packages are Available*
*For additional information on our PbïFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbïFree Package
PLCCï28
FN SUFFIX
CASE 776
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
MCxxxE416FNG
AWLYYWW
128
