ISL83699IR-T

7
FN6094.3
November 5, 2004
Detailed Description
The ISL83699 is a bidirectional, dual double-pole/
double-throw (DPDT) analog switch that offers precise
switching capability from a single 1.65V to 3.6V supply with
low on-resistance (0.26) and high speed operation
(t
ON
=10ns, t
OFF
= 7ns). The device is especially well suited
for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (45nA max), and the tiny
QFN and TSSOP packages. The ultra low on-resistance and
Ron flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (See
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (See Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R
ON
switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
Power-Supply Considerations
The ISL83699 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL83699 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V
the V
IH
level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (See Figure
15). The frequency response is very consistent over a wide
V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 16 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
FIGURE 8. OVERVOLTAGE PROTECTION
GND
V
COM
V
NO or NC
OPTIONAL PROTECTION
V+
IN
X
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL83699
8
FN6094.3
November 5, 2004
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Typical Performance Curves T
A
= 25°C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
R
ON
()
V
COM
(V)
01234
I
COM
= 100mA
0.2
0.25
0.3
0.35
0.4
0.45
V+ = 3V
V+ = 2.7V
V+ = 1.8V
V+ = 3.6V
R
ON
()
V
COM
(V)
00.511.522.53
V+ = 2.7V
I
COM
= 100mA
0.15
0.2
0.25
0.3
0.35
25°C
85°C
-40°C
00.511.52
R
ON
()
V
COM
(V)
0.2
0.25
0.3
0.35
0.4
0.45
0.5
85°C
-40°C
V+ = 1.8V
I
COM
= 100mA
25°C
00.511.522.53
Q (pC)
V
COM
(V)
-150
-100
-50
0
50
V+ = 1.8V
V+ = 3V
ISL83699
9
FN6094.3
November 5, 2004
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
FIGURE 15. FREQUENCY RESPONSE
FIGURE 16. CROSSTALK AND OFF ISOLATION
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN paddle connection: to ground or float)
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
Typical Performance Curves T
A
= 25°C, Unless Otherwise Specified (Continued)
t
ON
(ns)
V+ (V)
11.522.533.544.5
0
10
20
30
40
50
85°C
-40°C
25°C
t
OFF
(ns)
V+ (V)
1
1.5 2 2.5 3 3.5 4 4.5
0
5
10
15
20
25°C
85°C
-40°C
FREQUENCY (MHz)
0
-20
NORMALIZED GAIN (dB)
GAIN
PHASE
V+ = 3V
0
20
40
60
80
100
PHASE (DEGREES)
1 10 100 600
V
IN
= 0.2V
P-P
to 2V
P-P
R
L
= 50
FREQUENCY (Hz)
1K 100K 1M 100M 500M10K 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V+ = 3V
V+ (V)
V
INH
AND V
INL
(V)
11.522.533.544.5
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
V
INH
V
INL
ISL83699

ISL83699IR-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC SWITCH QUAD SPDT 16QFN
Lifecycle:
New from this manufacturer.
Delivery:
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