DOCSIS 3.0 Upstream Amplifier
MAX3518
6 _______________________________________________________________________________________
Detailed Description
Programmable-Gain Amplier
The programmable-gain amplifier (PGA) provides 63dB
of output level control in 1dB steps. The gain of the
PGA is determined by a 6-bit gain code (GC5–GC0)
programmed through the serial data interface (Tables
1 and 2). Specified performance is achieved when the
input is driven differentially.
Four power codes (PC1–PC0) allow the PGA to be used
with reduced bias current when distortion performance
can be relaxed. In addition, for each power code, bias
current is automatically reduced with gain code for
maximum efficiency.
The PGA features a differential Class A output stage
capable of driving four +58dBmV QPSK modulated
signals, or a single +64dBmV QPSK modulated signal
into a 75Ω load. This architecture provides superior
even-order distortion performance but requires that a
transformer be used to convert to a single-ended out-
put. In transmit-disable mode, the output amplifiers
are powered down, resulting in low output noise, while
maintaining impedance match.
3-Wire Serial Interface (SPI)
and Control Registers
The MAX3518 includes two programmable registers
for initializing the part and setting the gain and power
consumption. The 4 MSBs are address bits; the 8 least
significant bits (LSBs) are used for register data. Data is
shifted MSB first.
Note: The registers must be written 100µs after the
device is powered up, and no earlier. Once a new set
of register data is clocked in, the corresponding power
code and/or gain code does not take effect until TXEN
transitions from high to low.
Applications Information
Power Codes
The MAX3518 is designed to meet the stringent linearity
requirements of DOCSIS 3.0 using power code (PC) 3.
For DOCSIS 2.0, PC = 1 is recommended, which results
in substantial supply current reduction. The full range of
gain codes can be used in any power code. The gain
difference between power codes is typically less than
0.1dB.
Pin Description
PIN NAME FUNCTION
1, 5 GND Ground
2 IN+ Positive PGA Input
3 IN- Negative PGA Input
4, 11 N.C. No Connection. These pins must remain open.
6 SCLK Serial Interface Clock
7 SDA Serial Interface Data
8
CS
Serial Interface Enable
9 TXEN Transmit Enable. TXEN = high places the device in transmit mode.
10 V
CC
Supply Voltage for Serial Interface
12 OUT- Negative Output
13, 15, 16, 18,
19, 20
N.C. No Connection. Connect these pins to ground.
14 OUT+ Positive Output
17 V
CC
Supply Voltage for Programmable-Gain Amplifier (PGA)
— EP Ground
Table 1. Register Description
REGISTER
NAME
REGISTER
ADDRESS
DATA 8 BITS
B7 B6 B5 B4 B3 B2 B1 B0
Power/Gain 0000 PC2 PC1 GC5 GC4 GC3 GC2 GC1 GC0
Initialize 0001 0 0 0 0 0 0 0 0
