DOCSIS 3.0 Upstream Amplifier
MAX3518
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resistance on the secondary winding. Operating in a
75Ω system tends to shift the low-frequency edge of the
transformer bandwidth specification up by a factor of
1.5 due to primary inductance. Keep this in mind when
specifying a transformer.
Bias to the output stage is provided through the center
tap on the transformer primary. This greatly diminishes
the on/off transients present at the output when switch-
ing between transmit and transmit-disable modes.
Commercially available transformers typically have
adequate balance between half-windings to achieve
substantial transient cancellation.
Finally, keep in mind that transformer core inductance
varies with temperature. Adequate primary inductance
must be present to sustain broadband output capability
as temperatures vary.
Input Circuit
To achieve rated performance, the inputs of the
MAX3518 must be driven differentially with an appro-
priate input level. The differential input impedance
is 200Ω. Most applications require an anti-alias filter
preceding the device. The filter should be designed to
match this 200Ω impedance.
The MAX3518 has sufficient gain to produce an output
level of 64dBmV QPSK when driven with a +33dBmV input
signal. If an input level greater than +34dBmV is used, the
3rd-order distortion performance will degrade slightly.
Layout Issues
A well-designed printed circuit board (PCB) is an essen-
tial part of an RF circuit. For best performance, pay
attention to power-supply layout issues as well as the
output circuit layout.
No Connect Pins
Pins 4 and 11 must be left open, not connected to sup-
ply or ground or any other node in the circuit. Pins 13,
15, 16, 18, 19, and 20 should be connected to ground.
Output Circuit Layout
The differential implementation of the MAX3518 output
has the benefit of significantly reducing even-order
distortion, the most significant of which is 2nd-har-
monic distortion. The degree of distortion cancellation
depends on the amplitude and phase balance of the
overall circuit. It is important to keep the trace lengths
from the output pins equal.
Power-Supply Layout
For minimal coupling between different sections of the
IC, the ideal power-supply layout is a star configuration.
This configuration has a large-value decoupling capaci-
tor at the central power-supply node. The power-supply
traces branch out from this node, each going to a sepa-
rate power-supply node in the circuit. At the end of each
of these traces is a decoupling capacitor that provides
a very low impedance at the frequency of interest. This
arrangement provides local power-supply decoupling at
each power-supply pin. The power-supply traces must
be capable of carrying the maximum current without
significant voltage drop.
The output transformer center tap node, VCC_CT, must
be connected to supply through a 3Ω resistor to reduce
the supply voltage on OUT+ and OUT-. This resistor
must be rated to dissipate 250mW at +85°C.
Exposed Pad Thermal Considerations
The exposed pad (EP) of the MAX3518’s 20-pin TQFN
package provides a low thermal resistance path to the
die. It is important that the PCB on which the MAX3518
is mounted be designed to conduct heat from this con-
tact. In addition, the EP should be provided with a low-
inductance path to electrical ground.
It is recommended that the EP be soldered to a ground
plane on the PCB, either directly or through an array of
plated via holes.
Chip Information
PROCESS: SiGe BiCMOS
