2
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
0767E—12/14/07
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDD PWR Power su
l
, nominal 3.3V
2 SRC_IN IN 0.7 V Differential SRC TRUE in
ut
3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY in
ut
4 GND PWR Ground
in.
5 VDD PWR Power su
l
, nominal 3.3V
6 DIF_1 OUT 0.7V differential true clock out
uts
7 DIF_1# OUT 0.7V differential com
lement clock out
uts
8 OE_1 IN
Active high input for enabling outputs.
0 = tri-state out
uts, 1= enable out
uts
9 DIF_2 OUT 0.7V differential true clock out
uts
10 DIF_2# OUT 0.7V differential com
lement clock out
uts
11 VDD PWR Power su
l
, nominal 3.3V
12 BYPASS#/PLL IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = B
ass mode, 1= PLL mode
13 SCLK IN Clock
in of SMBus circuitr
, 5V tolerant.
14 SDATA I/O Data
in for SMBus circuitr
, 5V tolerant.
15 PD# IN
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
16 SRC_STOP# IN Active low in
ut to sto
diff out
uts.
17 HIGH_BW# IN
3.3V input for selecting PLL Band Width
0 = Hi
h, 1= Low
18 VDD PWR Power su
l
, nominal 3.3V
19 DIF_5# OUT 0.7V differential com
lement clock out
uts
20 DIF_5 OUT 0.7V differential true clock out
uts
21 OE_6 IN
Active high input for enabling outputs.
0 = tri-state out
uts, 1= enable out
uts
22 DIF_6# OUT 0.7V differential com
lement clock out
uts
23 DIF_6 OUT 0.7V differential true clock out
uts
24 VDD PWR Power su
l
, nominal 3.3V
25 GND PWR Ground
in.
26 IREF OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
27 GNDA PWR Ground
in for the PLL core.
28 VDDA PWR 3.3V power for the PLL core.
