4
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
0767E—12/14/07
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage 4.6 V
VDD_In 3.3V Logic Supply Voltage 4.6 V
V
IL
Input Low Voltage GND-0.5 V
V
IH
Input High Voltage V
DD
+0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
I
nput
ESD
protect
i
on
human body model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5% 2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
3.3 V +/-5%
GND
- 0.3
0.8 V
Input High Current
I
IH
V
IN
= V
DD
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
Operating Supply Current
I
DD3.3OP
Full Active, C
L
= Full load;
200 mA
all diff
p
airs driven 40 mA
all differential
p
airs tri-stated 12 mA
Input Frequency
3
F
i
V
DD
= 3.3 V
80
100/133
166/200
220 MHz 3
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
PLL Bandwidth when
PLL_BW=0
4MHz1
PLL Bandwidth when
PLL_BW=1
2MHz1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
1ms1,2
Modulation Fre
q
uenc
y
Trian
g
ular Modulation 30 33 kHz 1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Sto
p
# de-assertion
10 ns 1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall
Fall time of PD# and
SRC_STOP#
5ns1
Trise
Rise time of PD# and
SRC_STOP#
5ns2
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
See timin
g
dia
g
rams for timin
g
re
q
uirements.
I
DD3.3PD
3
Time from deassertion until out
p
uts are >200 mV
Input Capacitance
1
Input Low Current
Powerdown Current
PLL Bandwidth BW
5
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
0767E—12/14/07
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
1
V
O
= V
x
3000
1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross
Variation of crossin
g
over all
ed
g
es
140 mV 1
Lon
g
Accurac
y
pp
msee T
p
eriod min-max values 0
pp
m1,2
200MHz nominal 4.9985 5.0015 ns 2
200MHz s
p
read 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz s
p
read 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz s
p
read 7.4978 5.4000 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz s
p
read 9.9970 10.0533 ns 2
200MHz nominal 4.8735 ns 1,2
166.66MHz nominal/s
p
read 5.8732 ns 1,2
133.33MHz nominal/s
p
read 7.3728 ns 1,2
100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation
d-t
r
125 ps 1
Fall Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45 55 % 1
Skew
t
sk3
V
T
= 50%
50 ps 1
PLL mode,
Measurement from differential
wavefrom
50 ps 1
BYPASS mode as additive jitter 50 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on sin
g
le ended
signal using absolute value.
mV
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
TperiodAverage period
Absolute min period
T
absmin
Jitter, Cycle to cycle
t
jcyc-cyc
6
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
0767E—12/14/07
General SMBus serial interface information for the ICS9DB104
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address DC
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address DC
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operation
Slave Address DC
(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address DD
(h)
Index Block Read Operation
Slave Address DC
(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK

9DB104BFLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet