MC74HC174A
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V 55C to 25C 85C 125C Unit
V
IH
Minimum High–Level Input
Voltage
V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| 20 A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| 20 A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High–Level Output
Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| 20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
|I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low–Level Output
Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| 20 A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
|I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input Leakage Current V
IN
= V
CC
or GND 6.0 0.1 1.0 1.0 A
I
CC
Maximum Quiescent Supply
Current (per Package)
V
IN
= V
CC
or GND
I
OUT
= 0 A
6.0 4.0 40 160 A
9. Information on typical parametric values, along with high frequency or heavy load considerations, can be found in the ON Semiconductor
High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V 55C to 25C 85C 125C Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 4 and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 5 and 7)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
PLH
t
PHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 7)
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
t
TLH
t
THL
Maximum Output Transition Time, Any Output
(Figures 4 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
10.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance, per Enabled Output (Note 11) 62 pF
11. Used to determine the no–load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
