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2015-11-0004 PT0225-6 11/25/15
11
PT7C4302
Real-time Clock Module (3-wire Interface)
c) Single Byte Read
Figure 2 Single byte read
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK
cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written.
Additional SCLK cycles will transmit the same data bytes by PT7C4302 so long as RST remains high. This operation permits
continuous burst mode read capability. Also, the SDA pin is tri-stated upon each rising edge of SCLK. Data is output starting with
bit 0.
d) Single Byte Write
Figure 3 Signal byte write
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK
cycles. Additional SCLK cycles are ignored. Data is input starting with bit 0.
e) Burst Mode
Burst mode is specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (Address bits: A4 A3
A2 A1 A0 = 1 1 1 1 1 showed in Figure 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no
data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred.
If the number of transferred bytes is less than eight, the data will be ignored. However, when writing to RAM in burst mode, it is
not necessary to write all 31 bytes for the data to transfer. Each byte that is written will be transferred to RAM regardless of
whether all 31 bytes are written or not. Additional SCLK cycles are ignored.
Clock/Calendar Burst Mode
The clock/calendar command byte specifies burst mode operation. In this mode the first eight clock/calendar registers can be
consecutively read or written starting with bit 0 of address 0.
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the
eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read
from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an
update of the main registers during a read.
RAM Burst Mode
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written
starting with bit 0 of address 0.
Note: PT7C4302 use 94H, 96H as test mode address. Customer should not use the address.
