NSQA12VAW5T2G

NSQA6V8AW5T2 Series
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4
IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 3. IEC6100042 Spec
Figure 4. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test
Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0
020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
t
P
t
r
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE I
RSM
@ 8 ms
HALF VALUE I
RSM
/2 @ 20 ms
NSQA6V8AW5T2 Series
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5
Figure 6. Pulse Width
100
10
1
1 10 100 1000
t, TIME (ms)
P
pk
, PEAK SURGE POWER (W)
Figure 7. Power Derating Curve
T
A
, AMBIENT TEMPERATURE (°C)
1501251007550250
90
80
70
60
50
40
30
20
10
0
100
110
% OF RATED POWER OR I
PP
Figure 8. Reverse Leakage versus
Temperature
0.16
0.02
0
60 0 80 100
T, TEMPERATURE (°C)
I
R
, REVERSE LEAKAGE (mA)
40 20 604020
0.04
0.06
0.08
0.10
0.12
0.14
Figure 9. Capacitance
14
12
10
8
6
4
2
0
01 2 3 6
BIAS VOLTAGE (V)
T
A
= 25°C
TYPICAL CAPACITANCE (pF)
1 MHz FREQUENCY
45
6 V
12 V
V
F
, FORWARD VOLTAGE (V)
1.81.61.41.21.00.80.6
0.1
0.01
0.001
1
I
F
, FORWARD CURRENT (A)
T
A
= 25°C
Figure 10. Forward Voltage
NSQA6V8AW5T2 Series
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6
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A01 OBSOLETE. NEW STANDARD
419A02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B 1.15 1.350.045 0.053
C 0.80 1.100.031 0.043
D 0.10 0.300.004 0.012
G 0.65 BSC0.026 BSC
H --- 0.10---0.004
J 0.10 0.250.004 0.010
K 0.10 0.300.004 0.012
N 0.20 REF0.008 REF
S 2.00 2.200.079 0.087
B0.2 (0.008)
MM
12 3
45
A
G
S
D
5 PL
H
C
N
J
K
B
SC88A (SC705/SOT353)
CASE 419A02
ISSUE L
ǒ
mm
inches
Ǔ
SCALE 20:1
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
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NSQA12VAW5T2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors Low Cap. TVS Quad Array for ESD
Lifecycle:
New from this manufacturer.
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