87608I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 201610
CRYSTAL INPUT INTERFACE
The 87608I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
Figure 2. CRYSTAL INPUt INTERFACE
resonant crystal and were chosen to minimize the frequency
ppm error. The optimum C1 and C2 values can be slightly ad-
justed for optimum frequency accuracy.
C1
22p
X1
18pF Parallel Cry stal
C2
22p
XTAL 2
XTAL 1
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left fl oating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full
swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This confi guration requires
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
