87608I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20167
TABLE 7B. AC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 166.67 MHz
t(Ø) Static Phase Offset; NOTE 1 FREF = 25MHz -365 -105 160 ps
tsk(b) Bank Skew; NOTE 2, 6 60 ps
tsk(o) Output Skew; NOTE 3, 6 250 ps
tjit(cc) Cycle-to-Cycle Jitter; 6 170 ps
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7 20 ps
tsl(o) Slew Rate 1 4 v/ns
t
L
PLL Lock Time 10 ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle; NOTE 5 48 52 %
All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted.
NOTE 1: Defi ned as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable. Measured at V
DD
/2.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_IN. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 7: This parameter is defi ned as an RMS value.
