MC74AC646DWG

© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 7
1 Publication Order Number:
MC74AC646/D
MC74AC646, MC74ACT646
Octal Transceiver/Register
with 3-State Outputs
(Non-inverting)
The MC74AC646/74ACT646 consist of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated Figures 1 to 4.
Features
Independent Registers for A and B Buses
Multiplexed Real−Time and Stored Data Transfers
Choice of True and Inverting Data Paths
3−State Outputs
300 mil Slim Dual In−Line Package
Outputs Source/Sink 24 mA
ACT646 Has TTL Compatible Inputs
These are Pb−Free Devices
REAL TIME TRANSFER
A‐BUS TO B‐BUS
REAL TIME TRANSFER
B‐BUS TO A‐BUS
REG
REG REG REG
REG REG REG REG
B‐BUS B‐BUS
A‐BUS A‐BUS
B‐BUS B‐BUS
A‐BUS A‐BUS
STORAGE
FROM BUS TO REGISTER
TRANSFER
FROM REGISTER TO BUS
Figure 1. Figure 2.
Figure 3. Figure 4.
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MARKING DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
SO−24
DW SUFFIX
CASE 751E
ACT646
AWLYYWWG
1
24
AC646
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
MC74AC646, MC74ACT646
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2
PIN ASSIGNMENT
PIN FUNCTION
A
0
−A
7
Data Register Inputs
Data Register A Outputs
B
0
−B
7
Data Register B Inputs
Data Register B Outputs
CAB, CBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
DIR, G Output Enable Inputs
Figure 6. Logic Symbol
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
CAB
SAB
DIR
CBA
SBA
G
1 OF 8 CHANNELS
D
0
C
0
D
0
C
0
CAB
SAB
DIR
CBA
SBA
G
B
0
A
0
TO 7 OTHER CHANNELS
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 7. Logic Diagram
Figure 5. Pinout: 24−Lead Packages Conductors
(Top View)
1
CAB
2
SAB
3
DIR
4
A
0
5
A
1
6
A
2
7
A
3
8
A
4
9
A
5
10
A
6
11
A
7
12
GND
24 23 22 21 20 19 18 17 16 14 13
V
CC
CBA SBA G B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
15
MC74AC646, MC74ACT646
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3
FUNCTION TABLE
Inputs Data I/O*
Operation or Function
G DIR CAB CBA SAB SBA A
0
−A
7
B
0
−B
7
H
H
X
X
H or L H or L X
X
X
X
Input Input
Isolation
Store A and B Data
L
L
L
L
X
X
X
X
X
X
L
H
Output Input
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input Output
Real Time A Data to B Bus
Stored A Data to B Bus
*The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW−to−HIGH transition of the appropriate clock inputs.
NOTE: H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; = LOW−to−HIGH Transition

MC74AC646DWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Bus Transceivers Octal Transceiver Non-Inverting
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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