MAX7326
I
2
C Port Expander with 12 Push-Pull Outputs
and 4 Inputs
_______________________________________________________________________________________ 7
When the MAX7326 is read through the serial interface,
the actual logic levels at the ports are read back.
The four input ports offer latching transition detection
functionality. All input ports are continuously monitored
for changes. An input change sets 1 of 4 flag bits that
identify the changed input(s). All flags are cleared upon
a subsequent read or write transaction to the MAX7326.
A latching interrupt output, INT, is programmed to flag
input data changes on the four input ports through an
interrupt mask register. By default, data changes on
any input port force INT to a logic-low. The interrupt out-
put INT and all transition flags are deasserted when the
MAX7326 is next accessed through the serial interface.
Internal pullup resistors to V+ are selected by the
address select inputs, AD0 and AD2. Pullups are
enabled on the input ports in groups of two (see Table 2).
Initial Power-Up
On power-up, the transition detection logic is reset, and
INT is deasserted. The interrupt mask register is set to
0x3C, enabling the interrupt output for transitions on all
four input ports. The transition flags are cleared to indi-
cate no data changes. The power-up default states of
the 12 push-pull outputs are set according to the I
2
C
slave address selection inputs, AD0 and AD2 (see
Tables 2 and 3). Pullups are enabled on the input port
in groups of two (see Table 2).
Power-On Reset (POR)
The MAX7326 contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. When V+ rises above V
POR
(1.6V max), the
POR circuit releases the registers and 2-wire interface
for normal operation. When V+ drops below V
POR
, the
MAX7326 resets all output register contents to the POR
defaults (Tables 2 and 3).
RST
Input
The active-low RST input operates as a reset that voids
any I
2
C transaction involving the MAX7326 and forcing
the MAX7326 into the I
2
C STOP condition. The reset
action does not clear the interrupt output (INT).
Standby Mode
When the serial interface is idle, the MAX7326 automat-
ically enters standby mode, drawing minimal supply
current.
Slave Address, Power-Up Default
Logic Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7326
slave address and select which inputs have pullup
resistors. Pullups are enabled on the input ports in
groups of two (see Table 2).
The MAX7326 slave address is determined on each I
2
C
transmission, regardless of whether the transmission is
actually addressing the MAX7326. The MAX7326 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. This means that the
MAX7326 slave address can be configured dynamically
in the application without cycling the device supply.
On initial power-up, the MAX7326 cannot decode
address inputs AD0 and AD2 fully until the first I
2
C
transmission. This is important because the address
selection is used to determine the power-up logic state
(output low or I/O high), and whether pullups are
enabled. However, at power-up, the I
2
C SDA and SCL
bus interface lines are high impedance at the pins of
every device (master or slave) connected to the bus,
including the MAX7326. This is guaranteed as part of
the I
2
C specification. Therefore, when address inputs
AD0 and AD2 are connected to SDA or SCL during
power-up, they appear to be connected to V+. The port
PART
I
2
C
SLAVE
ADDRESS
INPUTS
INPUT
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION
MAX7323
110xxxx Up to 4
Up to 4 4
4 I/O, 4 output-only versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7328
MAX7329
0100xxx
0111xxx
Up to 8
Up to 8
8 open-drain I/O ports with nonlatching transition
detection interrupt and pullups on all ports.
Table 1. MAX7319–MAX7329 Family Comparison (continued)
MAX7326
I
2
C Port Expander with 12 Push-Pull Outputs
and 4 Inputs
8 _______________________________________________________________________________________
selection logic uses AD0 to select whether pullups are
enabled for ports I2 and I3, and to set the initial logic
level for those ports, and AD2 for ports I4 and I5. The
rule is that a logic-high, SDA, or SCL connection
selects the pullups and sets the default logic state to
high. A logic-low sets the default to low (Tables 2 and
3). This means that the port configuration is correct on
power-up for a standard I
2
C configuration, where SDA
or SCL are pulled up to V+ by the external I
2
C pullup
resistors.
The power-up default states of the 12 push-pull outputs
are set according to the I
2
C slave address selection
inputs, AD0 and AD2 (Tables 2 and 3).
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7326’s supply voltage, and if that pullup supply
rises later than the MAX7326’s supply, then SDA or SCL
may appear at power-up to be connected to GND. In
applications like this, use the four address combinations
that are selected by strapping address inputs AD0 and
AD2 to V+ or ground (shown in bold in Tables 2 and 3).
These selections are guaranteed to be correct at power-
up, independent of SDA and SCL behavior. If one of the
other 12 address combinations is used, an unexpected
combination of pullups might be asserted until the first
I
2
C transmission (to any device, not necessarily the
MAX7326) is put on the bus, and an unexpected combi-
nation of ports may initialize as logic-low outputs instead
of inputs or logic-high outputs.
Port Inputs
Port inputs switch at CMOS-logic levels as determined
by the expander’s supply voltage, and are overvoltage
tolerant to +6V, independent of the expander’s supply
voltage.
Port-Input Transition Detection
All four input ports are monitored for changes since the
expander was last accessed through the serial inter-
face. The state of the input ports is stored in an internal
“snapshot” register for transition monitoring. The snap-
shot is continuously compared with the actual input
conditions, and if a change is detected for any port
input, then an internal transition flag is set for that port.
The four port inputs are sampled (internally latched into
the snapshot register) and the old transition flags are
cleared during the I
2
C acknowledge of every MAX7326
read and write access. The previous port transition
flags are read through the serial interface as the sec-
ond byte of a 2-byte read sequence.
PIN
CONNECTION
DEVICE ADDRESS PORT POWER-UP DEFAULT
40k INPUT PULLUPS ENABLED
AD2
AD0 A6 A5 A4 A3 A2 A1 A0 O7 O6 I5 I4 I3 I2 O1 O0 O7 O6 I5 I4 I3 I2 O1
O0
SCL
GND110000011 0 0 YY
SCL
V+
110000111 1 1 YYYY
SCL
SCL110001011 1 1 YYYY
SCL
SDA110001111 1 1 YYYY
SDA
GND110010011 0 0 YY
SDA
V+
110010111 1 1 YYYY
SDA
SCL110011011 1 1 YYYY
SDA
SDA110011111 1 1 YYYY
GND
GND110100000 0 0
GND
V+
110100100 1 1 YY
GND
SCL110101000 1 1 YY
GND
SDA110101100 1 1 YY
V+
GND110110011 00 YY
V+ V+
110110111 11 YYYY
V+
SCL110111011 1 1 YYYY
V+
SDA110111111
Inputs
11
Pullups are not enabled for push-pull outputs.
Y YYY
Pullups are not enabled for push-pull outputs.
Table 2. MAX7326 Address Map for Ports O0, O1, I2–I5, O6, and O7
MAX7326
I
2
C Port Expander with 12 Push-Pull Outputs
and 4 Inputs
_______________________________________________________________________________________ 9
A long read sequence (more than 2 bytes) can be used
to poll the expander continuously without the overhead
of resending the slave address. If more than 2 bytes
are read from the expander, the expander repeatedly
returns the 2 bytes of input port data followed by the
transition flags. The inputs are repeatedly resampled
and the transition flags repeatedly reset for each pair of
bytes read. All changes that occur during a long read
sequence are detected and reported.
The MAX7326 includes a 4-bit interrupt mask register
that selects which inputs generate an interrupt upon
change. Each input’s transition flag is set when its input
changes, independent of the interrupt mask register
settings. The interrupt mask register allows the proces-
sor to be interrupted for critical events, while the inputs
and the transition flags can be polled periodically to
detect less-critical events.
The INT output is not reasserted during a read
sequence to avoid recursive reentry into an interrupt
service routine. Instead, if a data change occurs that
would normally cause the INT output to be set, the INT
assertion is delayed until the STOP condition. INT is not
reasserted upon a STOP condition if the changed input
data is read before the STOP occurs. The INT logic
ensures that unnecessary interrupts are not asserted,
yet data changes are detected and reported no matter
when the change occurs.
Transition-Detection Masks
The transition-detection logic incorporates a change
flag and an interrupt mask bit for each of the four input
ports. The four change flags can be read through the
serial interface, and the 4-bit interrupt mask is set
through the serial interface.
Each port’s change flag is set when that port’s input
changes, and the change flag remains set even if the
input returns to its original state. The port’s interrupt
mask determines whether a change on that input port
generates an interrupt. Enable interrupts for high-priority
inputs using the interrupt mask. The interrupt allows the
system to respond quickly to changes on these inputs.
Poll the MAX7326 periodically to monitor less-important
inputs. The change flags indicate whether a permanent or
transient change has occurred on any input since the
MAX7326 was last accessed.
PIN CONNECTION DEVICE ADDRESS OUTPUTS POWER-UP DEFAULT
AD2 AD0
A6 A5 A4 A3 A2 A1 A0 O15 O14 O13 O12 O11 O10 O9
O8
SCL GND 10100001
1
11000
0
SCL V+ 10100011
1
11111
1
SCL SCL 1 0 1 0 0 1 0 1
1
11111
1
SCL SDA 1 0 1 0 0 1 1 1
1
11111
1
SDA GND 10101001
1
11000
0
SDA V+ 10101011
1
11111
1
SDA SCL 1 0 1 0 1 1 0 1
1
11111
1
SDA SDA 1 0 1 0 1 1 1 1
1
11111
1
GND GND 10110000
0
00000
0
GND V+ 10110010
0
00111
1
GND SCL 10110100
0
00111
1
GND SDA 10110110
0
00111
1
V+ GND 10111001
1
11000
0
V+ V+ 10111011
1
11111
1
V+ SCL 10111101
1
11111
1
V+ SDA 10111111
1
11111
1
Table 3. MAX7326 Address Map for Outputs O8–O15

MAX7326ATG+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders I2C Port Expander w/12 P-P Out & 4 In
Lifecycle:
New from this manufacturer.
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