EMC1184-A-AIA Datasheet EMC1184-A-AIA, EMC1184-A-AIA-TR | P34-P36

Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Revision 1.0 (07-11-13) 34 SMSC EMC1184

DATASHEET

The Therm Limit Registers are used to determine whether a critical thermal event has occurred. If the

measured temperature exceeds the Therm Limit, the THERM pin is asserted. The limit setting must

match the chosen data format of the temperature reading registers.

Unlike the ALERT / THERM2 pin, the THERM pin cannot be masked. Additionally, the THERM pin will

be released once the temperature drops below the corresponding threshold minus the Therm

Hysteresis.

6.10 External Diode Fault Register 1Bh

The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the

Status Register to be set. This register is cleared when it is read.

Bit 3 - E3FLT - This bit is set if the External Diode 3 channel reported a diode fault.

Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault.

Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.

6.11 Channel Mask Register 1Fh

The Channel Mask Register controls individual channel masking. When a channel is masked, the

ALERT / THERM2 pin will not be asserted when the masked channel reads a diode fault or out of limit

error. The channel mask does not mask the

THERM pin.

Bit 3 - E3MASK - Masks the ALERT / THERM2pin from asserting when the External Diode 3 channel

is out of limit or reports a diode fault.

 ‘0’ (default) - The External Diode 3 channel will cause the ALERT / THERM2pin to be asserted if

it is out of limit or reports a diode fault.

21h R/W

Therm

Hysteresis

128 64 32 16 8 4 2 1

0Ah

(10°C)

30h R/W

External

Diode 3

Therm Limit

128 64 32 16 8 4 2 1

55h

(85°C)

Table 6.11 External Diode Fault Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

1Bh R-C

External

Diode Fault

- - - - E3FLT E2FLT E1FLT - 00h

Table 6.12 Channel Mask Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

1Fh R/W

Channel

Mask

----

MASK

INT

MASK

00h

Table 6.10 Therm Limit Registers (continued)

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

SMSC EMC1184 35 Revision 1.0 (07-11-13)

DATASHEET

 ‘1’ - The External Diode 3 channel will not cause the ALERT / THERM2pin to be asserted if it is

out of limit or reports a diode fault.

Bit 2 - E2MASK - Masks the ALERT / THERM2pin from asserting when the External Diode 2 channel

is out of limit or reports a diode fault.

 ‘0’ (default) - The External Diode 2 channel will cause the ALERT / THERM2pin to be asserted if

it is out of limit or reports a diode fault.

 ‘1’ - The External Diode 2 channel will not cause the ALERT / THERM2 pin to be asserted if it is

out of limit or reports a diode fault.

Bit 1 - E1MASK - Masks the ALERT / THERM2 pin from asserting when the External Diode 1 channel

is out of limit or reports a diode fault.

 ‘0’ (default) - The External Diode 1 channel will cause the ALERT / THERM2 pin to be asserted if

it is out of limit or reports a diode fault.

 ‘1’ - The External Diode 1 channel will not cause the ALERT / THERM2 pin to be asserted if it is

out of limit or reports a diode fault.

Bit 0 - INTMASK - Masks the ALERT / THERM2 pin from asserting when the Internal Diode

temperature is out of limit.

 ‘0’ (default) - The Internal Diode channel will cause the ALERT / THERM2 pin to be asserted if it

is out of limit.

 ‘1’ - The Internal Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out

of limit.

6.12 Consecutive ALERT Register 22h

The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must

be detected in consecutive measurements before the

ALERT / THERM2 or THERM pin is asserted.

Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.

An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in

consecutive measurements will increment the consecutive alert counter. The counters will also be reset

if no out-of-limit condition or diode fault condition occurs in a consecutive reading.

When the ALERT / THERM2 pin is configured as an interrupt, when the consecutive alert counter

reaches its programmed value, the following will occur: the STATUS bit(s) for that channel and the last

error condition(s) (i.e. E1HIGH, or E2LOW and/or E2FAULT) will be set to ‘1’, the

ALERT / THERM2

pin will be asserted, the consecutive alert counter will be cleared, and measurements will continue.

When the ALERT / THERM2 pin is configured as a comparator, the consecutive alert counter will

ignore diode fault and low limit errors and only increment if the measured temperature exceeds the

High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the

ALERT/

THERM2 pin will be asserted, but the counter will not be reset. It will remain set until the temperature

drops below the High Limit minus the Therm Hysteresis value.

For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1184 device, the high

limits are set at 70°C, and none of the channels are masked, the

ALERT / THERM2 pin will be

asserted after the following four measurements:

Table 6.13 Consecutive ALERT Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

22h R/W

Consecutive

ALERT

TIME

OUT

CTHRM[2:0] CALRT[2:0] - 70h

Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Revision 1.0 (07-11-13) 36 SMSC EMC1184

DATASHEET

1. Internal Diode reads 71°C and both external diodes read 69°C. Consecutive alert counter for INT

is incremented to 1.

2. Both the Internal Diode and External Diode 1 read 71°C and External Diode 2 reads 68°C.

Consecutive alert counter for INT is incremented to 2 and for EXT1 is set to 1.

3. The External Diode 1 reads 71°C and both the Internal Diode and External Diode 2 read 69°C.

Consecutive alert counters for INT and EXT2 are cleared and EXT1 is incremented to 2.

4. The Internal Diode reads 71°C and both external diodes read 71°C. Consecutive alert counter for

INT is set to 1, EXT2 is set to 1, and EXT1 is incremented to 3.

5. The Internal Diode reads 71°C and both the external diodes read 71°C. Consecutive alert counter

for INT is incremented to 2, EXT2 is set to 2, and EXT1 is incremented to 4. The appropriate status

bits are set for EXT1 and the ALERT / THERM2 pin is asserted. EXT1 counter is reset to 0 and

all other counters hold the last value until the next temperature measurement.

Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.

 ‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely

without the device resetting its SMBus protocol.

 ‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than t

TIMEOUT

the device will reset the SMBus protocol.

Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the

corresponding Therm Limit before the THERM pin is asserted. All temperature channels use this value

to set the respective counters. The consecutive Therm counter is incremented whenever any

measurement exceed the corresponding Therm Limit.

If the temperature drops below the Therm Limit, the counter is reset. If a number of consecutive

measurements above the Therm Limit occurs, the THERM pin is asserted low.

Once the THERM pin has been asserted, the consecutive therm counter will not reset until the

corresponding temperature drops below the Therm Limit minus the Therm Hysteresis value.

The bits are decoded as shown in Table 6.14. The default setting is 4 consecutive out of limit

conversions.

Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of

limit condition or diode fault before the ALERT / THERM2 pin is asserted. All temperature channels

use this value to set the respective counters. The bits are decoded as shown in Ta bl e 6.14. The default

setting is 1 consecutive out of limit conversion.

Table 6.14 Consecutive Alert / Therm Settings

210

NUMBER OF CONSECUTIVE OUT OF LIMIT

MEASUREMENTS

000

(default for CALRT[2:0])

001 2

011 3

111

(default for CTHRM[2:0])

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48

EMC1184-A-AIA

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Board Mount Temperature Sensors 1.8V SMBus Dual Tmp Sensor /w Alerts

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EMC1184-A-AIA

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