10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
02/02/2012
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-200 -166
Symbol Parameter Min. Max. Min. Max. Unit
fmax Clock Frequency — 200 — 166 MHz
tKC Cycle Time 5 — 6 — ns
tKH Clock High Time 2 — 2.5 — ns
tKL Clock Low Time 2 — 2.5 — ns
tKQ Clock Access Time — 3.1 — 3.5 ns
tKQX
(2)
Clock High to Output Invalid 1.5 — 1.5 — ns
tKQLZ
(2,3)
Clock High to Output Low-Z 1 — 1 — ns
tKQHZ
(2,3)
Clock High to Output High-Z — 3.0 — 3.4 ns
tOEQ Output Enable to Output Valid — 3.1 — 3.5 ns
tOELZ
(2,3)
Output Enable to Output Low-Z 0 — 0 — ns
tOEHZ
(2,3)
Output Disable to Output High-Z — 3.0 — 3.4 ns
tAS Address Setup Time 1.4 — 1.5 — ns
tWS Read/Write Setup Time 1.4 — 1.5 — ns
tCES Chip Enable Setup Time 1.4 — 1.5 — ns
tSE Clock Enable Setup Time 1.4 — 1.5 — ns
tADVS Address Advance Setup Time 1.4 — 1.5 — ns
tDS Data Setup Time 1.4 — 1.5 — ns
tAH Address Hold Time 0.4 — 0.5 — ns
tHE Clock Enable Hold Time 0.4 — 0.5 — ns
tWH Write Hold Time 0.4 — 0.5 — ns
tCEH Chip Enable Hold Time 0.4 — 0.5 — ns
tADVH Address Advance Hold Time 0.4 — 0.5 — ns
tDH Data Hold Time 0.4 — 0.5 — ns
tPDS ZZ High to Power Down — 2 — 2 cyc
tPUS ZZ Low to Power Down — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
