LTC3563
10
3563f
design. An additional 0.1µF to 1µF ceramic capacitor is
also recommended on V
IN
for high frequency decoupling,
when not using an all ceramic capacitor solution.
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfi ed, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement,
except for an all ceramic solution. The output ripple (ΔV
OUT
)
is determined by:
∆∆V I ESR
C
OUT L
OUT
≈+
1
8• ƒ
O
where f
O
is the switching frequency, C
OUT
is the output
capacitance and ΔI
L
is the inductor ripple current. For a fi xed
output voltage, the output ripple is highest at maximum
input voltage since ΔI
L
increases with input voltage.
If tantalum capacitors are used, it is critical that the capaci-
tors are surge tested for use in switching power supplies.
An excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. These are specially constructed and tested for low
ESR so they give the lowest ESR for a given volume. Other
capacitor types include Sanyo POSCAP, Kemet T510 and
T495 series, and Sprague 593D and 595D series. Consult
the manufacturer for other specifi c recommendations.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high
ripple current rating, high voltage rating and low ESR
are tempting for switching regulator use. However, the
ESR is so low that it can cause loop stability problems.
Since the LTC3563’s control loop does not depend on
the output capacitor’s ESR for stable operation, ceramic
capacitors can be used to achieve very low output ripple
and small circuit size. X5R or X7R ceramic capacitors are
recommended because these dielectrics have the best
temperature and voltage characteristics of all the ceramics
for a given value and size.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V
IN
pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part. For more information, see Application
Note 88. The recommended capacitance value to use is
10µF for both input and output capacitors.
APPLICATIO S I FOR ATIO
WUUU
Table 1. Representative Surface Mount Inductors
MANUFACTURER
PART NUMBER VALUE
(µH)
MAX DC
CURRENT
(A)
DCR
(Ω) SIZE (mm
3
)
Sumida CDRH2D11 2.2 0.780 0.098 3.2 × 3.2 × 1.2
CDRH3D16 2.2 1.2 0.075 3.8 × 3.8 × 1.8
CMD4D11 2.2 0.95 0.116 4.4 × 5.8 × 1.2
CDH2D09B 3.3 0.85 0.15 2.8 × 3 × 1
CLS4D09 4.7 0.75 0.15 4.9 × 4.9 × 1
Murata LQH32CN 2.2 0.79 0.097 2.5 × 3.2 × 1.55
LQH43CN 4.7 0.75 0.15 4.5 × 3.2 × 2.6
TDK IVLC453232 2.2 0.85 0.18 4.8 × 3.4 × 3.4
VLF3010AT-
2R2M1R0
2.2 1.0 0.12 2.8 × 2.6 × 1
LTC3563
11
3563f
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3563 circuits: 1) V
IN
quiescent current,
2) I
2
R loss and 3) switching loss. V
IN
quiescent current
loss dominates the power loss at very low load currents,
whereas the other two dominate at medium to high load
currents. In a typical effi ciency plot, the effi ciency curve
at very low load currents can be misleading since the
actual power loss is of no consequence as illustrated in
Figure 2.
1) The V
IN
quiescent current is the DC supply current given
in the Electrical Characteristics which excludes MOSFET
charging current. V
IN
current results in a small (<0.1%)
loss that increases with V
IN
, even at no load.
2) I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current fl ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (D) as follows:
R
SW
= (R
DS(ON)TOP
)(D) + (R
DS(ON)BOT
)(1 – D)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
3) The switching current is MOSFET gate charging current,
that results from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current out of
V
IN
that is typically much larger than the DC bias current.
In continuous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the internal top and bottom
MOSFET switches. The gate charge losses are proportional
to V
IN
and thus their effects will be more pronounced at
higher supply voltages.
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. The internal battery
and fuse resistance losses can be minimized by making
sure that C
IN
has adequate charge storage and very low
ESR at the switching frequency. Other losses include
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total ad-
ditional loss.
APPLICATIO S I FOR ATIO
WUUU
Figure 2. Power Loss vs Load Current
OUTPUT CURRENT (mA)
1
POWER LOSS (mW)
10
100
1000
0.1 10 100 1000
3563 F02
0.1
1
V
OUT
= 1.87V
V
OUT
= 1.28V
V
IN
= 3.6V
LTC3563
12
3563f
Thermal Considerations
In most applications the LTC3563 does not dissipate much
heat due to its high effi ciency. But in applications where the
LTC3563 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
To avoid the LTC3563 from exceeding the maximum
junction temperature, the user needs to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3563 with an output
voltage of 1.87V, an input voltage of 2.7V, a load current
of 500mA and an ambient temperature of 70°C. From
the typical performance graph of switch resistance, the
R
DS(ON)
of the P-channel switch at 70°C is approximately
0.7Ω and the R
DS(ON)
of the N-channel synchronous
switch is approximately 0.4Ω. The duty cycle in this case
is approximately 70%.
The series resistance looking into the SW pin is:
R
SW
= 0.7Ω (0.7) + 0.4Ω (0.3) = 0.61Ω
Therefore, for the power dissipated by the part is:
P
D
= I
LOAD
2
• R
SW
= 152.5mW
For the DFN package, the θ
JA
is 40°C/W. Thus, the junction
temperature of the regulator is:
T
J
= 70°C + (0.1525)(40) = 76.1°C
APPLICATIO S I FOR ATIO
WUUU
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
, generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching loads with large (>1µF) bypass capacitors.
The discharged bypass capacitors are effectively put in
parallel with C
OUT
, causing a rapid drop in V
OUT
. No regula-
tor can deliver enough current to prevent this problem, if
the switch connecting the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap
TM
controller is designed
specifi cally for this purpose and usually incorporates cur-
rent limit, short circuit protection and soft-start.
Design Example
As a design example, assume the LTC3563 is used in
a single lithium-ion battery-powered cellular phone ap-
plication. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.5A, but most of the time it will be in
standby mode, requiring only 2mA. Effi ciency at both
low and high load currents is important. Output voltage
is either 1.87V or 1.28V.

LTC3563EDC#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500mA, Monolithic Buck w/ Selectable Output
Lifecycle:
New from this manufacturer.
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