LTC3563
13
3563f
With this information we can calculate L using:
L
fI
V
V
V
L
OUT
OUT
IN
=
1
1
••
Substituting V
OUT
= 1.87V, V
IN
= 4.2V, ΔI
L
= 200mA and
f = 2.25MHz gives:
L
V
MHz mA
V
V
=
=
187
2 25 200
1
187
42
231
.
.•
•–
.
.
. µµH
With V V
L
V
MHz mA
OUT
=
=
128
128
2 25 200
1
12
.
.
.•
•–
.
88
42
198
V
V
µH
.
.
=
Choosing a vendor’s closest inductor value of 2.2µH results
in a maximum ripple current of:
For V V
I
V
MHz µH
V
OUT
L
=
=
187
187
225 22
1
187
.
.
.•.
•–
.
442
209 6
128
128
2
.
.
.
.
.
V
mA
For V V
I
V
OUT
L
=
=
=
225 2 2
1
128
42
179 8
MHz µH
V
V
mA
•.
•–
.
.
.
=
APPLICATIO S I FOR ATIO
WUUU
Hot Swap is a trademark of Linear Technology Corporation.
C
IN
will require an RMS current rating of at least
0.25A I
LOAD(MAX)
/2 at temperature and C
OUT
will require
ESR of less than 0.2Ω. In most cases, ceramic capacitors
will satisfy these requirements. Select C
OUT
= 10µF and
C
IN
= 10µF.
Figure 3 shows the complete circuit along with its effi ciency
curve, load step response and recommended layout.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3563. These items are also illustrated graphically
in Figure 3b. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
3. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
Figure 3a. Typical Application
V
IN
LTC3563
RUN
3563 F03
L
C
IN
C
OUT
SW
V
IN
2.7V TO 5.5V
V
OUT
V
OUT
V
SEL
GND
1.28V 1.87V
LTC3563
14
3563f
APPLICATIO S I FOR ATIO
WUUU
Figure 3b. Layout Diagram
Figure 3c. Effi ciency Curve
Figure 3d. Load Step
RUN
SW
V
OUT
V
IN
GND
4
5
GND
GND
GND
V
OUT
3563 F03b
V
IN
VIA TO V
OUT
L
6
3
2
1
V
SEL
C
IN
C
OUT
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.1 10 100 1000
3563 G17
0
1
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
V
OUT
= 1.87V
FIGURE 3a CIRCUIT
I
L
500mA/DIV
I
LOAD
500mA/DIV
V
IN
= 3.6V
V
OUT
= 1.87V
I
LOAD
= 0A TO 500mA
20µs/DIV
3563 G04
V
OUT
100mV/DIV
AC COUPLED
LTC3563
15
3563f
U
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.05
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
1.37 ±0.05
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
0.25 ± 0.05
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.675 ±0.05
2.50 ±0.05
PACKAGE
OUTLINE
0.50 BSC
PIN 1
CHAMFER OF
EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3563EDC#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500mA, Monolithic Buck w/ Selectable Output
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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