4©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
AC Electrical Characteristics
Table 4A. AC Characteristics, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay, NOTE 1 ƒ 350MHz 1.7 2.0 2.3 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 500 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range
(637kHz – 10MHz)
0.21 ps
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2V 100 250 400 ps
odc Output Duty Cycle
ƒ 166MHz 45 50 55 %
166MHz < ƒ 350MHz 40 50 60 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay, NOTE 1 ƒ 350MHz 1.9 2.2 2.5 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 500 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range
(637kHz – 10MHz)
0.21 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 550 ps
odc Output Duty Cycle
ƒ 250MHz 45 50 55 %
250MHz < ƒ 350MHz 40 50 60 %
5©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Offset Frequency (Hz)
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.21ps (typical)
6©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Differential Input Level
3.3V Output Rise/Fall Time
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
Part-to-Part Skew
2.5V Output Rise/Fall Time
SCOPE
Qx
GND
V
DD
1.65V±0.15V
-1.65V±0.15V
V
DD
GND
CLK
nCLK
V
CMR
Cross Points
V
PP
0.8V
2V
2V
0.8V
t
R
t
F
Q0
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
t
sk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
Qx
Qy
20%
80%
80%
20%
t
R
t
F
Q0

83021AMILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Differential-to-LVCM OS Translator
Lifecycle:
New from this manufacturer.
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