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83021AMILFT

P1-P3P4-P6P7-P9P10-P12
7©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
Parameter Measurement Information, continued
Propagation Delay Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 1. Single-Ended Signal Driving Differential Input
nCLK
Q0
CLK
Q0
V_REF
Single Ended Clock Input
V
DD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
8©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP
and
V
CMR
input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 2C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 2B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60Ω
2.5V
3.3V
R1
120Ω
R2
120Ω
R3
120
Ω
R4
120
Ω
9©2015 Integrated Device Technology, Inc December 14, 2015
83021I Datasheet
Reliability Information
Table 5.
JA
vs. Air Flow Table for an 8 Lead SOIC
Transistor Count
The transistor count for 83021I is: 416
Pin-to-pin compatible with the MC100EPT21
Package Outline and Package Dimensions
Package Outline - M Suffix for 8 Lead SOIC Table 6. Package Dimensions
Reference Document: JEDEC Publication 95, MS-012
JA
by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 123°C/W 110°C/W 99°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 103°C/W 94°C/W 89°C/W
150 il (N B d ) SOIC
All Dimensions in Millimeters
Symbol Minimum Maximum
N 8
A 1.35 1.75
A1 0.10 0.25
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 Basic
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
0° 8°
P1-P3P4-P6P7-P9P10-P12

83021AMILFT

Mfr. #:
Buy 83021AMILFT
Manufacturer:
IDT
Description:
Clock Buffer Differential-to-LVCM OS Translator
Lifecycle:
New from this manufacturer.
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