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FM93C46 Rev. D.1
FM93C46 1024-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
The Erase all instruction will program all locations to a logical 1
state. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. After
inputting the last bit of data (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer
Erase
All cycle diagram.
Note:
The Fairchild CMOS EEPROMs do not require an ERASE or ERASE ALL
instruction prior to the WRITE or WRITE ALL instruction, respectively. The
ERASE and ERASE ALL instructions are included to maintain compatibility with
earlier technology EEPROMs.Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is cleared
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer
Clearing Ready Status
diagram.
Related Document
Application Note: AN758 - Using Fairchilds MICROWIRE EE-
PROM.
8
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FM93C46 Rev. D.1
FM93C46 1024-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
t
CSS
SYNCHRONOUS DATA TIMING
CS
SK
DI
DO (Data Read)
DO (Status Read)
Valid Status
t
DIS
t
DIH
t
PD
t
DH
t
SV
t
SKH
t
SKL
t
CSH
t
DF
t
DF
t
PD
Valid
Input
Valid
Input
Valid
Output
Valid
Output
CS
SK
DI
DO
High - Z
Dummy
Bit
1 1 0 A5 A4 A1 A0
0
D15 D1 D0
t
CS
NORMAL READ CYCLE (READ)
Address
Bits(6)
Start
Bit
Opcode
Bits(2)
93C46:
Address bits pattern -> User defined
Timing Diagrams
Address
Bits(6)
CS
SK
DI
DO
High - Z
WRITE ENABLE CYCLE (WEN)
Start
Bit
93C46:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Opcode
Bits(2)
1 0 0 A5 A4 A1 A0
t
CS
9
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FM93C46 Rev. D.1
FM93C46 1024-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Timing Diagrams (Continued)
Address
Bits(6)
CS
SK
DI
DO
High - Z
WRITE DISABLE CYCLE (WDS)
Start
Bit
93C46:
Address bits pattern -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Opcode
Bits(2)
1 0 0 A5 A4 A1 A0
t
CS
Address
Bits(6)
Data
Bits(16)
CS
SK
DI
DO
High - Z
t
CS
WRITE CYCLE (WRITE)
Start
Bit
93C46:
Address bits pattern -> User defined
Data bits pattern -> User defined
Opcode
Bits(2)
1 0 1 A5 A4 A1 A0 D15 D14 D1 D0
Busy
Ready
t
WP
Address
Bits(6)
Data
Bits(16)
CS
SK
DI
DO
High - Z
t
CS
WRITE ALL CYCLE (WRALL)
Start
Bit
93C46:
Address bits pattern -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> User defined
Opcode
Bits(2)
1 0 0 A5 A4 A1 A0 D15 D14 D1 D0
Busy
Ready
t
WP

FM93C46M8

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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