AD7453
Rev. B | Page 18 of 20
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, then 100.5 SCLKs occur between interrupts
and subsequently between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7453 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7453. The
CS
input allows easy interfacing between the
TMS320C5x/C54x and the AD7453 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKx (Tx serial clock) and
FSx (Tx frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1 and TXM
= 1. The format bit, FO, may be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7453. The connection diagram is shown in Figure 29. For
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling.
AD7453*
TMS320C5x/
C54x*
CLKx
DR
FSx
FSR
SCLK
SDATA
CS
CLKR
03155-A-029
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 29. Interfacing to the TMS320C5x/C54x
AD7453 to DSP56xxx
The connection diagram in Figure 30 shows how the AD7453
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word
length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To
implement the power-down mode on the AD7453, the word
length can be changed to eight bits by setting Bits WL1 = 0 and
WL0 = 0 in CRA. For signal processing applications, it is
imperative that the frame synchronization signal from the
DSP56xxx provide equidistant sampling.
AD7453*
DSP56xxx*
SCLK
SRD
SR2
SCLK
SDATA
CS
03155-A-030
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 30. Interfacing to the DSP56xxx
