AD7453
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
V
DD
to GND –0.3 V to +7 V
V
IN+
to GND –0.3 V to V
DD
+ 0.3 V
V
IN–
to GND –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to V
DD
+ 0.3 V
V
REF
to GND –0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
1
±10 mA
Operating Temperature Range
Commercial (A, B Version) –40°C to +85°C
Storage Temperature Range –65°C to +85°C
Junction Temperature 150°C
θ
JA
Thermal Impedance 211.5°C/W (SOT-23)
θ
JC
Thermal Impedance 91.99°C/W (SOT-23)
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infrared (15 secs) 220°C
ESD 1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Transient currents of up to 100 mA will not cause SCR latch-up.
1.6mA I
OL
200µAI
OH
1.6V
TO OUTPUT
PIN
C
L
25pF
03155-A-003
Figure 3. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7453
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD
1
SCLK
2
SDATA
3
CS
4
V
REF
V
IN+
V
IN–
GND
8
7
6
5
03155-A-004
AD7453
TOP VIEW
(Not to Scale)
Figure 4. Pin Function Descriptions
Table 4. Pin Function Descriptions
Mnemonic Function
V
REF
Reference Input for the AD7453. An external reference in the range 100 mV to V
DD
must be applied to this input. The specified
reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.1 µF.
V
IN+
Noninverting Analog Input.
V
IN–
Inverting Input. This pin sets the ground reference point for the V
IN+
input. Connect to ground or to a dc offset to provide a
pseudo ground.
GND
Analog Ground. Ground reference point for all circuitry on the AD7453. All analog input signals and any external reference
signal should be referred to this GND voltage.
CS
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7453 and
framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7453 is provided on this output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four leading zeros followed
by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
V
DD
Power Supply Input. V
DD
is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF
tantalum capacitor.
AD7453
Rev. B | Page 8 of 20
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fun-
damental. Noise is the sum of all nonfundamental signals up to
half the sampling frequency (f
S
/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7453, it is defined as
1
2
6
2
5
2
4
2
3
2
2
V
VVVVV
THD
++++
= log20)dB(
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it is a noise
peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at the sum and difference frequencies of mfa ± nfb
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb),
(fa + 2fb), and (fa − 2fb).
The AD7453 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is the input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (000...000 to 000...001)
from the ideal (i.e., AGND + 1 LSB)
Gain Error
This is the deviation of the last code transition (111...110 to
111...111) from the ideal (i.e., VREF – 1 LSB), after the offset
error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track and hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 100 mV p-p sine wave applied to the
ADC V
DD
supply of frequency f
S
. The frequency of this input
varies from 1 kHz to 1 MHz.
PSRR(dB) = 10log(Pf/Pf
S
)
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency f
S
in the ADC output.

AD7453ARTZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC ADC 12BIT DFF 600KSPS SOT23-8
Lifecycle:
New from this manufacturer.
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