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X40431S14I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
16
FN8251.1
May 24, 2006
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh
General Purpose Memory Array Configuration
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x = 0 is for Array, x = 1 is for Control Register or
Fault Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 14. X40430, X40431, X40434, X40435
Addressing
– last bit of the slave command byte is a R/W
bit. The
R/W
bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W
bit is a one,
then a read operation is selected. A zero selects a
write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET
Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 15. Current Address Read Sequence
.
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
S
t
a
r
t
S
t
o
p
Slave
Address
Data
SDA Bus
Signals from
the Slave
Signals from
the Master
1
A
C
K
1010 00
X40430, X40431, X40434, X40435
17
FN8251.1
May 24, 2006
Figure 16. Random Address Read Sequence
Figure 17. Sequential Read Sequence
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
101 00
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
X40430, X40431, X40434, X40435
18
FN8251.1
May 24, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on any pin with
respect to V
SS
...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10s) .................... 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
*See Ordering Info
Temperature Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Version
Chip Supply
Voltage
Monitored*
Voltages
X40430, X40431 2.7V to 5.5V 1.7V to 5.5V
X40434, X40435 2.7V to 5.5V 1.0V to 5.5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol Parameter Min Typ
(4)
Max Unit Test Conditions
I
CC1
(1)
Active Supply Current (V
CC
) Read 1.5 mA V
IL
= V
CC
x 0.1
V
IH
= V
CC
x 0.9,
f
SCL
= 400kHz
I
CC2
(1)
Active Supply Current (V
CC
) Write 3.0 mA
I
SB1
(1)(6)
Standby Current (V
CC
) AC (WDT off) 6 10 µA V
IL
= V
CC
x 0.1
VIH =
V
CC
x 0.9
f
SCL
, f
SDA
= 400kHz
I
SB2
(2)(6)
Standby Current (V
CC
) DC (WDT on) 25 30 µA V
SDA
= V
SCL
= V
CC
Others = GND or V
CC
I
LI
Input Leakage Current (SCL, MR,
WP)
10 µA V
IL
= GND to V
CC
I
LO
Output Leakage Current (SDA, V2-
FAIL, V3FAIL, WDO, RESET)
10 µA V
SDA
= GND to V
CC
Device is in Standby
(2)
V
IL
(3)
Input LOW Voltage (SDA, SCL, MR,
WP)
-0.5 V
CC
x 0.3 V
V
IH
(3)
Input HIGH Voltage (SDA, SCL, MR,
WP)
V
CC
x 0.7 V
CC
+ 0.5 V
V
HYS
(6)
Schmitt Trigger Input Hysteresis
• Fixed input level
•
V
CC
related level
0.2
.05 x V
CC
V
V
V
OL
Output LOW Voltage (SDA, RE-
SET/RESET
, LOWLINE, V2FAIL,
V3FAIL
, WDO)
0.4 V I
OL
= 3.0mA (2.7-5.5V)
I
OL
= 1.8mA (2.7-3.6V)
V
OH
Output (RESET, LOWLINE) HIGH
Voltage
V
CC
– 0.8
V
CC
– 0.4
VI
OH
= -1.0mA (2.7-5.5V)
I
OH
= -0.4mA (2.7-3.6V)
X40430, X40431, X40434, X40435
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

X40431S14I-B

Mfr. #:
Buy X40431S14I-B
Manufacturer:
Renesas / Intersil
Description:
IC VOLT MON TRPL EEPROM 14-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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