AD9708
–9–
REV. B
voltage. Figure 17 shows a buffered singled-ended output con-
figuration in which the op amp, U1, performs an I-V conversion
on the AD9708 output current. U1 provides a negative unipolar
output voltage and its full-scale output voltage is simply the
product of R
FB
and I
OUTFS
. The full-scale output should be set
within U1’s voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac distortion performance may
result with a reduced I
OUTFS
, since the signal current U1 will be
required to sink and will be subsequently reduced. Note, the ac
distortion performance of this circuit at higher DAC update
rates may be limited by U1’s slewing capabilities.
AD9708
22
IOUTA
IOUTB
21
C
OPT
200V
U1
V
OUT
= I
OUTFS
3 R
FB
I
OUTFS
= 10mA
R
FB
200V
Figure 17. Unipolar Buffered Voltage Output
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The positive output compliance range is
slightly dependent on the full-scale output current, I
OUTFS
. It
degrades slightly from its nominal 1.25 V for an I
OUTFS
= 20 mA
to 1.00 V for an I
OUTFS
= 2 mA. Applications requiring the
AD9708’s output (i.e., V
OUTA
and/or V
OUTB
) to extend up to its
output compliance range should size R
LOAD
accordingly. Operation
beyond this compliance range will adversely affect the AD9708’s
linearity.
The differential voltage, V
DIFF
, existing between V
OUTA
and
V
OUTB
may also be converted to a single-ended voltage via a
transformer or differential amplifier configuration. Refer to the
DIFFERENTIAL OUTPUT CONFIGURATION section for
more information.
DIGITAL INPUTS
The AD9708’s digital input consists of eight data input pins and
a clock input pin. The 8-bit parallel data inputs follow standard
positive binary coding where DB7 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). The digital
interface is implemented using an edge-triggered master slave
latch. The DAC output is updated following the rising edge of
the clock as shown in Figure 1 and is designed to support a
clock rate as high as 125 MSPS. The clock can be operated at
any duty cycle that meets the specified latch pulsewidth. The
setup-and-hold times can also be varied within the clock cycle as
long as the specified minimum times are met; although the
location of these transition edges may affect digital feedthrough
and distortion performance.
The digital inputs are CMOS compatible with logic thresholds,
V
THRESHOLD
set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2 (±20%)
Figure 18 shows the equivalent digital input circuit for the data
and clock inputs. The sleep mode input is similar, except that
it contains an active pull-down circuit, thus ensuring that the
AD9708 remains enabled if this input is left disconnected. The
internal digital circuitry of the AD9708 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage, V
OH(MAX)
,
of the TTL drivers. A DVDD of 3 V to 3.3 V will typically
ensure upper compatibility of most TTL logic families.
Figure 18. Equivalent Digital Input
Since the AD9708 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum
setup-and-hold times of the AD9708 as well as its required min/
max input logic level thresholds. Typically, the selection of the
slowest logic family that satisfies the above conditions will result
in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9708
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
data feedthrough. For longer run lengths and high data update
rates, strip line techniques with proper termination resistors
should be considered to maintain “clean” digital inputs. Also,
operating the AD9708 with reduced logic swings and a corre-
sponding digital supply (DVDD) will also reduce data feedthrough.
The external clock driver circuitry should provide the AD9708
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. However, the clock input could also be
driven by via a sine wave, which is centered around the digital
threshold (i.e., DVDD/2), and meets the min/max logic threshold.
This may result in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. Note, at higher sampling rates the 20% tolerance
of the digital logic threshold should be considered since it will
affect the effective clock duty cycle and subsequently cut into
the required data setup-and-hold times.
SLEEP MODE OPERATION
The AD9708 has a power-down function that turns off the
output current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures the AD9708 remains enabled if
this input is left disconnected. The SLEEP input with active
pull-down requires <40 µA of drive current.
The power-up and power-down characteristics of the AD9708
are dependent on the value of the compensation capacitor con-
nected to COMP2 (Pin 23). With a nominal value of 0.1 µF, the
AD9708 takes less than 5 µs to power down and approximately
3.25 ms to power back up.
