DYNAMIC SPECIFICATIONS
P
arameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
) 100 125 MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
35 ns
Output Propagation Delay (t
PD
)1ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
1
2.5 ns
Output Fall Time (10% to 90%)
1
2.5 ns
Output Noise (I
OUTFS
= 20 mA) 50 pA/Hz
Output Noise (I
OUTFS
= 2 mA) 30 pA/Hz
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion Ratio
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz 50 dB
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz 50 dB
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz 48 dB
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz 50 dB
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz 45 dB
Total Harmonic Distortion
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz –67 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz –67 –62 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz –59 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz –64 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz –48 dBc
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz 68 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz 62 68 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz 63 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz 67 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz 50 dBc
NOTES
1
Measured single ended into 50 load.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
P
arameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5pF
Input Setup Time (t
S
)2.0ns
Input Hold Time (t
H
)1.5ns
Latch Pulsewidth (t
LPW
)
3.5 ns
Specifications subject to change without notice.
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0–DB7
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Single-Ended Output, IOUTA, 50 Doubly
Terminated, unless otherwise noted)
AD9708
–3–
REV. B
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
AD9708
–4–
REV. B
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Units
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead TSSOP
θ
JA
= 97.9°C/W
θ
JC
= 14.0°C/W
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9708
NC = NO CONNECT
(MSB) DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
NC
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9708 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin No. Name Description
1 DB7 Most Significant Data Bit (MSB).
2–7 DB6–DB1 Data Bits 1–6.
8 DB0 Least Significant Data Bit (LSB).
9–14, 25 NC No Internal Connection.
15 SLEEP Power-Down Control Input. Active
High. Contains active pull-down circuit,
thus may be left unterminated if not
used.
16 REFLO Reference Ground when Internal 1.2 V
Reference Used. Connect to AVDD to
disable internal reference.
17 REFIO Reference Input/Output. Serves as
reference input when internal reference
disabled (i.e., Tie REFLO to AVDD).
Serves as 1.2 V reference output when
internal reference activated (i.e., Tie
REFLO to ACOM). Requires 0.1 µF
capacitor to ACOM when internal
reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node.
Add 0.1 µF to AVDD for optimum
performance.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output.
Full-scale current when all data bits
are 0s.
22 IOUTA DAC Current Output. Full-scale
current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver
Circuitry. Decouple to ACOM with
0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to
+5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to
+5.5 V).
28 CLOCK Clock Input. Data latched on positive
edge of clock.
ORDERING GUIDE
Temperature Package Package
Model Range Descriptions Options*
AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9708ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9708-EB Evaluation Board
*R = Small Outline IC; RU = Thin Small Outline IC.
WARNING!
ESD SENSITIVE DEVICE
AD9708
–5–
REV. B
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
DVDD
DCOM
RETIMED
CLOCK
OUTPUT*
DIGITAL
DATA
TEKTRONIX
AWG-2021
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50V
20pF
50V
20pF
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
+1.20V REF
REFLO
REF IO
FS ADJ
50pF
COMP1
0.1mF
CURRENT
SOURCE
ARRAY
+5V
AVDD
SEGMENTED
SWITCHES
LATCHES
DVDD
DCOM
CLOCK
SLEEP
IOUTA
IOUTB
COMP2
ACOM
0.1mF
+5V
R
SET
2kV
0.1mF
AD9708
50V
Figure 2. Basic AC Characterization Test Setup

AD9708AR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 8-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
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