MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
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Detailed Description
The
Typical Application Circuit
shows a typical connec-
tion using the MAX16020. OUT powers the static ran-
dom-access memory (SRAM). If V
CC
is greater than the
reset threshold (V
TH
), or if V
CC
is lower than V
TH
, but
higher than V
BATT
, V
CC
connects to OUT. If V
CC
is lower
than V
TH
and V
CC
is less than V
BATT
, BATT connects to
OUT (see the
Functional Diagrams
). In battery-backup
mode, an internal MOSFET connects the backup battery
to OUT. The on-resistance of the MOSFET is a function of
backup-battery voltage and temperature.
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of the RAM. With a backup battery
installed at BATT, the MAX16016/MAX16020/MAX16021
automatically switch the RAM to the backup power when
V
CC
falls. The MAX16016/MAX16020/MAX16021 have a
BATTON output that goes high when in battery-backup
mode. These devices require two conditions before
switching to battery-backup mode:
1) V
CC
must be below the reset threshold.
2) V
CC
must be below V
BATT
.
Table 3 lists the status of the inputs and outputs in bat-
tery-backup mode. The device does not power up if the
only voltage source is on BATT. OUT only powers up
from V
CC
at startup.
CE Signal Gating
The MAX16020/MAX16021 provide internal gating of
CE signals to prevent erroneous data from being written
to CMOS RAM in the event of a power failure or
brownout. During normal operation, the CE gate is
enabled and passes all CE transitions. When the reset
output asserts, this path becomes disabled, preventing
erroneous data from corrupting the CMOS RAM.
CEOUT is pulled up to OUT through an internal current
source. The 1.5ns propagation delay from CEIN to
CEOUT allows the devices to be used with most µPs
and high-speed DSPs.
During normal operation (reset not asserted), CEIN is
connected to CEOUT through a low on-resistance
transmission gate. If CEIN is high when a reset asserts,
CEOUT remains high regardless of any subsequent
transition on CEIN during the reset event.
If CEIN is low when reset asserts, CEOUT is held low
for 12µs to allow completion of the read/write operation.
After the 12µs delay expires, CEOUT goes high and
stays high regardless of any subsequent transitions on
CEIN during the reset event. When CEOUT is disconnect-
ed from CEIN, CEOUT is actively pulled up to OUT.
The propagation delay through the CE circuitry
depends on both the source impedance of the drive to
CEIN and the capacitive loading at CEOUT. Minimize
the capacitive load at CEOUT to minimize the propaga-
tion delay, and use a low output-impedance driver.
Low-Line Output (
LL
)
The low-line comparator monitors V
CC
with a threshold
voltage typically 2.5% higher than the reset threshold
(see Table 2). LL asserts prior to a reset condition during
a brownout condition. On power-up, LL deasserts after
the reset output. LL can be used to provide a nonmask-
able interrupt (NMI) to the µP when the voltage begins to
fall to initiate an orderly software shutdown routine.
Manual Reset Input
Many µP-based products require manual reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. For the MAX16016/MAX16020/
MAX16021, a logic-low on MR asserts RESET/RESET.
RESET/RESET remains asserted while MR is low. When
MR goes high RESET/RESET deasserts after a minimum
of 145ms (t
RP
). MR has an internal 30kΩ pullup resistor to
V
CC
. MR can be driven with TTL/CMOS logic levels or
with open-drain/collector outputs. Connect a normally
open momentary switch from MR to GND to create a
manual reset function; external debounce circuitry is not
required. If MR is driven from a long cable or the device is
used in a noisy environment, connect a 0.1µF capacitor
from MR to GND to provide additional noise immunity.
Table 3. Input and Output Status in
Battery-Backup Mode
