LTC1287
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Figures 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time
for the reference to settle. Even at the maximum CLK
rate of 500kHz most references and op amps can be
made to settle within the 2µs bit time. For example an
LT1790 with a 4.7µF bypass capacitor will settle
adequately.
Reduced Reference Operation
The effective resolution of the LTC1287 can be in-
creased by reducing the input span of the converter.
The LTC1287 exhibits good linearity over a range of
reference voltages (seeTypical Performance Charac-
teristics curves of Change in Linearity vs Reference
Voltage). Care must be taken when operating at low
values of V
REF
because of the reduced LSB step size and
the resulting higher accuracy requirement placed on
the converter. Offset and Noise are factors that must be
considered when operating at low V
REF
values.
Offset with Reduced V
REF
The offset of the LTC1287 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size
of the LSB is reduced. The Typical Performance Charac-
teristics curve of Unadjusted Offset Error vs Reference
Voltage shows how offset in LSBs is related to reference
voltage for a typical value of V
OS
. For example a V
OS
of
0.1mV, which is 0.2LSB with a 2.5V reference becomes
0.4LSB with a 1.25 reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
or by offsetting the –IN input to the LTC1287.
Noise with Reduced V
REF
The total input referred noise of the LTC1287 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This
noise is insignificant with a 2.5V reference input but will
become a larger fraction of an LSB as the size of the LSB
is reduced. The Typical Performance Characteristics
Figure 14. Poor Reference Settling Can Cause A/D Errors
Figure 13. Adequate Reference Settling
HORIZONTAL: 1µs/DIV
VERTICAL: 0.5mV/DIV
VERTICAL: 0.5mV/DIV
HORIZONTAL: 10µs/DIV
conversion (every CLK cycle) a capacitive current spike
will be generated on the reference pin by the A/D. These
current spikes settle quickly and do not cause a prob-
lem. If slow settling circuitry is used to drive the
reference input, take care to insure that transients
caused by these current spikes settle completely during
each bit test of the conversion.
Figure 12. Reference Input Equivalent Circuit
R
ON
8pF – 40pF
LTC1287
REF+
R
OUT
V
REF
EVERY CLK CYCLE
14
13
GND
LTC 1287 F12
14
LTC1287
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curve of Noise Error vs Reference Voltage shows the
LSB contribution of this 200µV of noise.
For operation with a 2.5V reference, the 200µV noise is
only 0.32LSB peak-to-peak. Here the LTC1287 noise
will contribute virtually no uncertainty to the output
code. For reduced references, the noise may become a
significant fraction of an LSB and cause undesirable
jitter in the output code. For example, with a 1.25V
reference, this 200µV noise is 0.64LSB peak-to-peak.
This will reduce the range of input voltages over which
a stable output code can be achieved by 0.64LSB. Now
averaging readings may be necessary.
This noise data was taken in a very clean test fixture.
Any setup induced noise (noise or ripple on V
CC
, V
REF
or V
IN
) will add to the internal noise. The lower the
reference voltage used, the more critical it becomes to
have a noise-free setup.
Overvoltage Protection
Applying signals to the LTC1287’s analog inputs that
exceed the positive supply or that go below ground will
degrade the accuracy of the A/D and possibly damage
the device. For example this condition would occur if a
signal is applied to the analog inputs before power is
applied to the LTC1287. Another example is the input
source operating from different supplies of larger value
than the LTC1287. These conditions should be pre-
vented either with proper supply sequencing or by use
of external circuitry to clamp or current limit the input
source. There are two ways to protect the inputs. In
Figure 15 diode clamps from the inputs to V
CC
and GND
are used. The second method is to put resistors in
series with the analog inputs for current limiting. Limit
the current to 15mA per channel. The +IN input can
accept a resistor value of 1k but the –IN input cannot
accept more than 200 when clocked at its maximum
clock frequency of 500kHz. If the LTC1287 is clocked at
the maximum clock frequency and 200 is not enough
to current limit the input source then the clamp diodes
are recommended (Figures 16 and 17). The reason for
the limit on the resistor value is the MSB bit test is
affected by the value of the resistor placed at the –IN
input (see discussion on Analog Inputs and the Typical
Performance Characteristics curve of Maximum CLK
Frequency vs Source Resistance).
If V
CC
and V
REF
are not tied together, then V
CC
should
be turned on first, then V
REF
. If this sequence cannot be
met, connecting a diode from V
REF
to V
CC
is recom-
mended (see Figure 18).
Because a unique input protection structure is used on
the digital input pins, the signal levels on these pins can
exceed the device V
CC
without damaging the device.
Figure 17. Overvoltage Protection for Inputs
+3V
LTC1287 F17
+IN
GND
V
REF
D
OUT
CLK
V
CC
CS
–IN
LTC1287
1N4148 DIODES
1k
Figure 16. Overvoltage Protection for Inputs
+3V
LTC1287 F16
+IN
GND
V
REF
D
OUT
CLK
V
CC
CS
–IN
200
1k
LTC1287
Figure 15. Overvoltage Protection for Inputs
+3V
LTC1287 F15
+IN
GND
V
REF
D
OUT
CLK
V
CC
CS
–IN
1N4148 DIODES
LTC1287
LTC1287
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A “Quick Look” Circuit for the LTC1287
Users can get a quick look at the function and timing of
the LTC1287 by using the following simple circuit
(Figure 19). V
REF
is tied to V
CC
. V
IN
is applied to the +IN
input and the –IN input is tied to the ground plane. CS
is driven at 1/32 the clock rate by the 74HC393 and D
OUT
outputs the data. The output data from the D
OUT
pin can
be viewed on an oscilloscope that is set up to trigger on
the falling edge of CS (Figure 20). Note the LSB data is
partially clocked out before CS goes high.
Figure 19. "Quick Look" Circuit for the LTC1287
CS
D
OUT
CLK
VERTICAL: 5V/DIV
HORIZONTAL: 5µs/DIV
Figure 20. Scope Trace of the LTC1287 “Quick Look” Circuit
Showing A/D Output 1010101010 (AAA
HEX
)
LSB
(B0)
NULL
BIT
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of circuits as described herein will not infringe on existing patent rights.
+3V
LTC1287 F18
1N4148
+2.5V
+IN
GND
V
REF
D
OUT
CLK
V
CC
CS
–IN
LTC1287
Figure 18
MSB
(B11)
LSB DATA
(B1)
TO OSCILLOSCOPE
LTC1287 F19
0.1µF
V
IN
f/32
+3V
CLOCK IN
500kHz
22µF TANTALUM
74HC393
A1
CLR1
1QA
1QB
1QC
1QD
GND
VCC
A2
CLR2
2QA
2QB
2QC
2QD
+
f
V
REF
D
OUT
CLK
V
CC
+IN
GND
CS
–IN
LTC1287

LTC1287BCN8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V 12-Bit Single Input, with S/H
Lifecycle:
New from this manufacturer.
Delivery:
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