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LT3083MPFE#TRPBF

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LT3083
13
3083fa
APPLICATIONS INFORMATION
Figure 5. Parallel Devices
effective value as low as 1μF to 2μF for the DC bias voltage
applied and over the operating temperature range. The X5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress. In a
ceramic capacitor, the stress can be induced by vibrations
in the system or thermal transients.
Paralleling Devices
Higher output current is obtained by paralleling multiple
LT3083s together. Tie the individual SET pins together and
tie the individual IN pins together. Connect the outputs in
common using small pieces of PC trace as ballast resistors
to promote equal current sharing. PC trace resistance in
mΩ/inch is shown in Table 2. Ballasting requires only a
tiny area on the PCB.
Table 2. PC Board Trace Resistance
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
2 27.1 13.6
Trace resistance is measured in mΩ/in
The worst-case room temperature offset, only ±4mV
(DD-PAK, T Packages) between the SET pin and the OUT
pin, allows the use of very small ballast resistors.
As shown in Figure 5, each LT3083 has a small 10mΩ
ballast resistor, which at full output current gives better
than 80% equalized sharing of the current. The external
Figure 3. Ceramic Capacitor DC Bias Characteristics
Figure 4. Ceramic Capacitor Temperature Characteristics
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3083 F03
20
0
–20
–40
–60
–80
–100
0
4
8
10
2 6
12
14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3083 F04
–25 0
50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
+
–
LT3083
V
IN
V
CONTROL
OUT
SET
10mΩ
+
–
LT3083
V
IN
V
IN
4.8V
TO 20V
V
OUT
3.3V
6A
V
CONTROL
OUT
10µF
10µF
SET
33k
3083 F05
10mΩ
LT3083
14
3083fa
APPLICATIONS INFORMATION
resistance of 10mΩ (5mΩ for the two devices in paral-
lel) only adds about 30mV of output regulation drop at
an output of 6A. With an output voltage of 3.3V, this only
adds 1% to the regulation. Of course, paralleling more
than two LT3083s yields even higher output current.
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output difference is high.
Quieting the Noise
The LT3083 offers numerous noise performance advan-
tages. Every linear regulator has its sources of noise. In
general, a linear regulator’s critical noise source is the
reference. In addition, consider the error amplifier’s noise
contribution along with the resistor divider’s noise gain.
Many traditional low noise regulators bond out the voltage
reference to an external pin (usually through a large value
resistor) to allow for bypassing and noise reduction. The
LT3083 does not use a traditional voltage reference like
other linear regulators. Instead, it uses a 50µA reference
current. The 50µA current source generates noise current
levels of 3.16pA/√Hz (1nA
RMS
) over the 10Hz to 100kHz
bandwidth). The equivalent voltage noise equals the RMS
noise current multiplied by the resistor value.
The SET pin resistor generates spot noise equal to √4kTR
(k = Boltzmann’s constant, 1.38 • 10
–23
J/°K, and T is abso-
lute temperature) which is RMS summed with the voltage
noise. If the application requires lower noise performance,
bypass the voltage setting resistor with a capacitor to GND.
Note that this noise-reduction capacitor increases start-up
time as a factor of the RC time constant.
The LT3083 uses a unity-gain follower from the SET pin
to the OUT pin. Therefore, multiple possibilities exist
(besides a SET pin resistor) to set output voltage. For
example, using a high accuracy voltage reference from
SET to GND removes the errors in output voltage due to
reference current tolerance and resistor tolerance. Active
driving of the SET pin is acceptable.
The typical noise scenario for a linear regulator is that the
output voltage setting resistor divider gains up the noise
reference, especially if V
OUT
is much greater than V
REF
.
The LT3083’s noise advantage is that the unity gain follower
presents no noise gain whatsoever from the SET pin to the
output. Thus, noise figures do not increase accordingly.
Error amplifier noise is typically 126.5nV/√Hz (40µV
RMS
)
over the 10Hz to 100kHz bandwidth). The error amplifier’s
noise is RMS summed with the other noise terms to give
a final noise figure for the regulator.
Curves in the Typical Performance Characteristics sec-
tion show noise spectral density and peak-to-peak noise
characteristics for both the reference current and error
amplifier over the 10Hz to 100kHz bandwidth.
Load Regulation
The LT3083 is a floating device. No ground pin exists on
the packages. Thus, the IC delivers all quiescent current
and drive current to the load. Therefore, it is not possible
to provide true remote load sensing. The connection resis-
tance between the regulator and the load determines load
regulation performance. The data sheet’s load regulation
specification is Kelvin sensed at the package’s pins. Nega-
tive-side sensing is a true Kelvin connection by returning
the bottom of the voltage setting resistor to the negative
side of the load (see Figure 6).
Connected as shown, system load regulation is the sum
of the LT3083’s load regulation and the parasitic line
resistance multiplied by the output current. To minimize
load regulation, keep the positive connection between the
regulator and load as short as possible. If possible, use
large diameter wire or wide PC board traces.
+
–
LT3083
IN
V
CONTROL
OUT
3080 F06
SET
R
SET
R
P
PARASITIC
RESISTANCE
R
P
R
P
LOAD
Figure 6. Connections for Best Load Regulation
LT3083
15
3083fa
APPLICATIONS INFORMATION
Thermal Considerations
The LT3083’s internal power and thermal limiting circuitry
protects itself under overload conditions. For continuous
normal load conditions, do not exceed the 125°C maximum
junction temperature. Carefully consider all sources of
thermal resistance from junction-to-ambient. This includes
(but is not limited to) junction-to-case, case-to-heat sink
interface, heat sink resistance or circuit board-to-ambient
as the application dictates. Consider all additional, adjacent
heat generating sources in proximity on the PCB.
Surface mount packages provide the necessary heat
sinking by using the heat spreading capabilities of the
PC board, copper traces, and planes. Surface mount heat
sinks, plated through-holes and solder-filled vias can also
spread the heat generated by power devices.
Junction-to-case thermal resistance is specified from the
IC junction to the bottom of the case directly, or the bottom
of the pin most directly in the heat path. This is the lowest
thermal resistance path for heat flow. Only proper device
mounting ensures the best possible thermal flow from this
area of the packages to the heat sinking material.
Note that the exposed pad of the DFN and TSSOP pack-
ages and the tab of the DD-PAK and TO-220 packages
are electrically connected to the output (V
OUT
).
Tables 3 through 5 list thermal resistance as a function
of copper areas on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm. Layers are not
connected electrically or thermally.
Table 3. DF Package, 12-Lead DFN
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2500mm
2
2500mm
2
2500mm
2
18°C/W
1000mm
2
2500mm
2
2500mm
2
22°C/W
225mm
2
2500mm
2
2500mm
2
29°C/W
100mm
2
2500mm
2
2500mm
2
35°C/W
*Device is mounted on topside.
Table 4. FE Package, 16-Lead TSSOP
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2500mm
2
2500mm
2
2500mm
2
16°C/W
1000mm
2
2500mm
2
2500mm
2
20°C/W
225mm
2
2500mm
2
2500mm
2
26°C/W
100mm
2
2500mm
2
2500mm
2
32°C/W
*Device is mounted on topside.
Table 5. Q Package, 5-Lead DD-PAK
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2500mm
2
2500mm
2
2500mm
2
13°C/W
1000mm
2
2500mm
2
2500mm
2
14°C/W
125mm
2
2500mm
2
2500mm
2
16°C/W
*Device is mounted on topside.
T Package, 5-Lead TO-220
Thermal Resistance (Junction-to-Case) = 3°C/W
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
PCB layers, copper weight, board layout and thermal vias
affect the resultant thermal resistance. Tables 3 through 5
provide thermal resistance numbers for best-case 4-layer
boards with 1oz internal and 2oz external copper. Modern,
multilayer PCBs may not be able to achieve quite the same
level performance as found in these tables.
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, a V
CONTROL
voltage of 3.3V ±10%, an IN voltage of 1.5V ±5%, output
current range from 10mA to 3A and a maximum ambient
temperature of 50°C, what will the maximum junction
temperature be for the DD-PAK on a 2500mm
2
board with
topside copper of 1000mm
2
?
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LT3083MPFE#TRPBF

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Buy LT3083MPFE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators Adjustable 3A Single Resistor Low Dropout Regulator
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