87974I Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 26, 20169
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 87974I
provides separate power supplies to isolate any high
switching noise from the outputs to the internal PLL. V
DD
,
V
DDA
, and V
DDOx
should be individually connected to the
power supply plane through vias, and bypass capacitors
should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each V
DDA
pin. The
10Ω resistor can also be replaced by a ferrite bead.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10 μF
.01μF
3.3V
.01μF
V
DD
APPLICATION INFORMATION
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left fl oating. We recommend
that there is no trace attached.
