874003AGI-02LF Datasheet 874003AGI-02LF, 874003AGLF, 874003AGI-02LFT | P7-P9

IDT

™

/ ICS

™

PCI EXPRESS™ JITTER ATTENUATOR 7 ICS874003AGI-02 REV A MAY 1, 2013

ICS874003I-02

PCI EXPRESS™ JITTER ATTENUATOR

APPLICATION INFORMATION

Figure 2

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V and R2/

R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLK

nCLK

VDD

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. The ICS874003I-02 provides sepa-

rate power supplies to isolate any high switching noise from the

outputs to the internal PLL. V

, V

DDA

, and V

DDO

should be indi-

vidually connected to the power supply plane through vias, and

bypass capacitors should be used for each pin. To achieve opti-

mum jitter performance, power supply isolation is required.

Fig-

ure 1

illustrates how a 10Ω resistor along with a 10μF and a

0.01μF bypass capacitor should be connected to each V

CCA

pin.

FIGURE 1. POWER SUPPLY FILTERING

10Ω

DDA

10μF

.01μF

3.3V

.01μF

IDT

™

/ ICS

™

PCI EXPRESS™ JITTER ATTENUATOR 8 ICS874003AGI-02 REV A MAY 1, 2013

ICS874003I-02

PCI EXPRESS™ JITTER ATTENUATOR

FIGURE 3C. CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3B. CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

SWING

and V

must meet the V

and V

CMR

input requirements. Figures 3A to 3D show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

FIGURE 3A. CLK/NCLK INPUT DRIVEN BY

ICS LVHSTL DRIVER

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example in

Figure 3A,

the input termination applies for ICS LVHSTL

drivers. If you are using an LVHSTL driver from another vendor,

use their termination recommendation.

INPUTS:

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, we

recommend that there is no trace attached.

50Ω

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50Ω

3.3V

50Ω

LVPE

Diff

nti

3.3V

100Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50Ω

IDT

™

/ ICS

™

PCI EXPRESS™ JITTER ATTENUATOR 9 ICS874003AGI-02 REV A MAY 1, 2013

ICS874003I-02

PCI EXPRESS™ JITTER ATTENUATOR

100 Ohm Differiential Transmission Line

100

3.3V

LVDS_Driv er

3.3V

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

LVDS DRIVER T ERMINATION

A general LVDS inteface is shown in

Figure 4.

In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near the

receiver input. For a multiple LVDS outputs buffer, if only partial

outputs are used, it is recommended to terminate the

unused outputs.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

874003AGI-02LF

Mfr. #:

Buy 874003AGI-02LF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner PCI EXPRESS JITTER ATTENUATOR

Lifecycle:

New from this manufacturer.

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874003AGI-02LF

874003AGI-02LF

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