49FCT3805EPYGI

4
INDUSTRIAL TEMPERATURE RANGE
IDT49FCT3805D/E
3.3V CMOS DUAL 1-TO-5 CLOCK DRIVER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 3805D
(3,4)
Symbol Parameter Conditions
(1)
Min.
(2)
Max. Unit
t
PLH Propagation Delay CL = 15pF 1 3 ns
tPHL INA to OAn, INB to OBn f 133MHz
tR Output Rise Time (0.8V to 2V) 1.5 ns
tF Output Fall Time (2V to 0.8V) 1.5 ns
tSK(O) Same device output pin to pin skew
(5)
270 ps
tSK(P) Pulse skew
(6,9)
270 ps
tSK(PP) Part to part skew
(7)
550 ps
t
PZL Output Enable Time 5.2 ns
tPZH OEA to OAn, OEB to OBn
tPLZ Output Disable Time 5.2 ns
tPHZ OEA to OAn, OEB to OBn
fMAX Input Frequency 133 MHz
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(P), and tSK(O) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
5. Skew measured between all outputs under identical transitions and load conditions.
6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions.
7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature.
8. Airflow of 1m/s is recommended for frequencies above 133MHz.
9. This parameter is measured using f = 1MHz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 3805E
(3,4)
Symbol Parameter Conditions
(1,8)
Min.
(2)
Max. Unit
tPLH Propagation Delay CL = 15pF 0.5 2.5 ns
tPHL INA to OAn, INB to OBn f 166MHz
tR Output Rise Time (0.8V to 2V) 1 ns
tF Output Fall Time (2V to 0.8V) 1 ns
tSK(O) Same device output pin to pin skew
(5)
200 ps
tSK(P) Pulse skew
(6,9)
270 ps
tSK(PP) Part to part skew
(7)
550 ps
t
PZL Output Enable Time 5.2 ns
tPZH OEA to OAn, OEB to OBn
tPLZ Output Disable Time 5.2 ns
tPHZ OEA to OAn, OEB to OBn
fMAX Input Frequency 166 MHz
5
IDT49FCT3805D/E
3.3V CMOS DUAL 1-TO-5 CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
tPLH1
OUTPUT 1
OUTPUT 2
tSK(o)
tPLH2
3V
0V
V
OH
1.5V
1.5V
V
OL
VOH
1.5V
V
OL
INPUT
tPHL1
tPHL2
tSK(o)
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
CL
VOUT
VCC
Pulse
Generator
D.U.T
V
IN
RT
RL
VCC
Pulse
Generator
D.U.T
V
IN
RT
CL
6V
GND
VOUT
RL
500
500
Open
CL = 15pF Test Circuit
TEST CIRCUITS AND WAVEFORMS
Enable and Disable Time Circuit
Test Switch
Disable Low 6V
Enable Low
Disable High GND
Enable High
SWITCH POSITION
Output Skew - tSK(O)
TEST CONDITIONS
Symbol VCC = 3.3V ±0.3V Unit
CL 15 pF
RT ZOUT of pulse generator
RL 33
tR / tF 1 (0V to 3V or 3V to 0V) ns
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
6
INDUSTRIAL TEMPERATURE RANGE
IDT49FCT3805D/E
3.3V CMOS DUAL 1-TO-5 CLOCK DRIVER
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
V
OH
VOL
SWITCH
CLOSED
SWITCH
OPEN
VOH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
VOH
VOL
1.5V
1.5V
ENABLE DISABLE
INPUT
tPLH1
PACKAGE 1
OUTPUT
t
SK(PP)
tPLH2
1.5V
V
OL
tPHL2
tSK(PP) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
PACKAGE 2
OUTPUT
3V
0V
V
OH
1.5V
1.5V
V
OL
VOH
tPHL1
3V
0V
VOH
tPLH tPHL
VOL
1.5V
1.5V
tR
tF
2.0V
0.8V
INPUT
OUTPUT
3V
0V
VOH
tPLH tPHL
VOL
1.5V
1.5V
INPUT
OUTPUT
tSK(P) = |tPLH - tPLH|
V
OL
tSK(PP)
Enable and Disable Times
Part-to-Part Skew - tSK(PP)
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
Propagation Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew
Part-to-Part Skew is for the same package and speed grade.

49FCT3805EPYGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 3.3V Dual 1:5 Clock Driver
Lifecycle:
New from this manufacturer.
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