LTC3836EGN#PBF Datasheet LTC3836EGN#PBF, LTC3836EUFD#TRPBF, LTC3836EGN#TRPBF | P10-P12

LTC3836

3836fb

OPERATION

(Refer to Functional Diagram)

Main Control Loop

The LTC3836 uses a constant-frequency, current mode

architecture with the two controllers operating 180 degrees

out-of-phase. During normal operation, the top external

power MOSFET is turned on when the clock for its chan-

nel sets the RS latch, and turned off when the current

comparator (I

CMP

) resets the latch. The peak inductor

current at which I

CMP

resets the RS latch is determined

by the voltage on the I

pin, which is driven by the output

of the error ampliﬁ er (EAMP). The V

pin receives the

output voltage feedback signal from an external resistor

divider. This feedback signal is compared to the internal

0.6V reference voltage by the EAMP. When the load current

increases, it causes a slight decrease in V

relative to the

0.6V reference, which in turn causes the I

voltage to

increase until the average inductor current matches the

new load current. While the top N-channel MOSFET is off,

the bottom N-channel MOSFET is turned on until either

the inductor current starts to reverse, as indicated by the

current reversal comparator, I

RCMP

, or the beginning of

the next cycle.

Shutdown, Soft-Start and Tracking Start-Up

(RUN/SS and TRACK/SS2 Pins)

The LTC3836 is shut down by pulling the RUN/SS pin

low. In shutdown, all controller functions are disabled and

the chip draws only 6.5μA. The TG and BG outputs are

held low (off) in shutdown. Releasing RUN/SS allows an

internal 0.65μA current source to charge up the RUN/SS

pin. When the RUN/SS pin reaches 0.65V, the LTC3836’s

two controllers are enabled.

The start-up of V

OUT1

is controlled by the LTC3836’s

internal soft-start. During soft-start, the error ampliﬁ er

EAMP compares the feedback signal V

FB1

to the internal

soft-start ramp (instead of the 0.6V reference), which rises

linearly from 0V to 0.6V in about 1ms. This allows the

output voltage to rise smoothly from 0V to its ﬁ nal value,

while maintaining control of the inductor current.

The 1ms soft-start time can be increased by con-

necting the optional external soft-start capacitor C

between the RUN/SS and SGND pins. As the RUN/SS

pin continues to rise linearly from approximately 0.65V

to 1.3V (being charged by the internal 0.65μA current

source), the EAMP regulates the V

FB1

proportionally

from 0V to 0.6V.

The start-up of V

OUT2

is controlled by the voltage on the

TRACK/SS2 pin. When the voltage on the TRACK/SS2

pin is less than the 0.6V internal reference, the LTC3836

regulates the V

FB2

voltage to the TRACK/SS2 pin voltage

instead of the 0.6V reference. This allows the TRACK/SS2

pin to be used to program a soft-start by connecting an

external capacitor from the TRACK/SS2 pin to SGND.

An internal 1μA pull-up current charges this capacitor,

creating a voltage ramp on the TRACK/SS2 pin. As the

TRACK/SS2 voltage rises linearly from 0V to 0.6V (and

beyond), the output voltage V

OUT2

rises smoothly from

zero to its ﬁ nal value.

Alternatively, the TRACK/SS2 pin can be used to cause the

start-up of V

OUT2

to “track” that of another supply. Typi-

cally, this requires connecting to the TRACK/SS2 pin an

external resistor divider from the other supply to ground

(see Applications Information section).

When the RUN/SS pin is pulled low to disable the

LTC3836, or when V

drops below its undervoltage

lockout threshold, the TRACK/SS2 pin is pulled low by

an internal MOSFET. When in undervoltage lockout, both

controllers are disabled and the external MOSFETs are

held off.

Light Load Operation (Pulse-Skipping or Continuous

Conduction) (SYNC/FCB Pin)

The LTC3836 can be enabled to enter high efﬁ ciency pulse-

skipping operation or forced continuous conduction mode

at low load currents. To select pulse-skipping operation, tie

the SYNC/FCB pin to a DC voltage above 0.6V (e.g., V

To select forced continuous operation, tie the SYNC/FCB

to a DC voltage below 0.6V (e.g., SGND).

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the I

pin. The main N-channel MOSFET

is turned on every cycle (constant-frequency) regardless

of the I

pin voltage. In this mode, the efﬁ ciency at light

loads is lower than in pulse-skipping operation. However,

continuous mode has the advantages of lower output ripple

and less interference with audio circuitry.

LTC3836

3836fb

OPERATION

(Refer to Functional Diagram)

When the SYNC/FCB pin is tied to a DC voltage above

0.6V or when it is clocked by an external clock source

to use the phase-locked loop (see Frequency Selection

and Phase-Locked Loop), the LTC3836 operates in PWM

pulse-skipping mode at light loads. In this mode, the

current comparator I

CMP

may remain tripped for several

cycles and force the main N-channel MOSFET to stay off

for the same number of cycles. The inductor current is

not allowed to reverse, though (discontinuous operation).

This mode, like forced continuous operation, exhibits low

output ripple as well as low audio noise and reduced RF

interference. However, it provides low current efﬁ ciency

higher than forced continuous mode. During start-up or

a short-circuit condition (V

FB1

or V

FB2

≤ 0.54V), the

LTC3836 operates in pulse-skipping mode (no cur-

rent reversal allowed), regardless of the state of the

SYNC/FCB pin.

Short-Circuit Protection

When an output is shorted to ground (V

< 0.12V), the

switching frequency of that controller is reduced to one-

ﬁ fth of the normal operating frequency. The other controller

maintains regulation in pulse-skipping mode.

The short-circuit threshold on V

FB2

is based on the smaller

of 0.12V and a fraction of the voltage on the TRACK/SS2

pin. This also allows V

OUT2

to start up and track V

OUT1

more easily. Note that if V

OUT1

is truly short-circuited

OUT1

= V

FB1

= 0V), then the LTC3836 will try to regulate

OUT2

to 0V if a resistor divider on V

OUT1

is connected to

the TRACK/SS pin.

Output Overvoltage Protection

As a further protection, the overvoltage comparator (OV)

guards against transient overshoots, as well as other more

serious conditions that may overvoltage the output. When

the feedback voltage on the V

pin has risen 13.33% above

the reference voltage of 0.6V, the main N-channel MOSFET

is turned off and the synchronous N-channel MOSFET is

turned on until the overvoltage is cleared.

Frequency Selection and Phase-Locked Loop (PLLLPF

and SYNC/FCB Pins)

The selection of switching frequency is a tradeoff between

efﬁ ciency and component size. Low frequency opera-

tion increases efﬁ ciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3836’s controllers can

be selected using the PLLLPF pin.

If the SYNC/FCB is not being driven by an external clock

source, the PLLLPF can be ﬂ oated, tied to V

or tied to

SGND to select 550kHz, 750kHz or 300kHz respectively.

A phase-locked loop (PLL) is available on the LTC3836

to synchronize the internal oscillator to an external clock

source that is connected to the SYNC/FCB pin. In this case,

a series RC should be connected between the PLLLPF pin

and SGND to serve as the PLL’s loop ﬁ lter. The LTC3836

phase detector adjusts the voltage on the PLLLPF pin to

align the turn-on of controller 1’s top MOSFET to the ris-

ing edge of the synchronizing signal. Thus, the turn-on

of controller 2’s top MOSFET is 180 degrees out-of-phase

with the rising edge of the external clock source.

The typical capture range of the LTC3836’s phase-locked

loop is from approximately 200kHz to 1MHz, and is guar-

anteed over temperature between 250kHz and 850kHz.

In other words, the LTC3836’s PLL is guaranteed to lock

to an external clock source whose frequency is between

250kHz and 850kHz.

Dropout Operation

Each top MOSFET driver is biased from the ﬂ oating boot-

strap capacitor C

, which normally recharges during each

off cycle through an external diode when the top MOSFET

turns off. If the input voltage V

decreases to a voltage

close to V

OUT

, the loop may enter dropout and attempt to

turn on the top MOSFET continuously. The dropout detec-

tor detects this and forces the top MOSFET off for about

200ns every fourth cycle to allow C

to recharge.

LTC3836

3836fb

OPERATION

(Refer to Functional Diagram)

Undervoltage Lockout

To prevent operation of the external MOSFETs below safe

input voltage levels, an undervoltage lockout is incorpo-

rated in the LTC3836. When the input supply voltage (V

)

drops below 2.25V, the external MOSFETs and all internal

circuitry are turned off except for the undervoltage block,

which draws only a few microamperes.

Peak Current Sense Voltage Selection and Slope

Compensation (IPRG1 and IPRG2 Pins)

When a controller is operating below 20% duty cycle,

the peak current sense voltage (between the SENSE

and

SW pins) allowed across the main N-channel MOSFET is

determined by:

V

SENSE(MAX)

ITH

– 0.7V

()

where A is a constant determined by the state of the

IPRG pins. Floating the IPRG pin selects A = 1;

tying IPRG to V

selects A = 5/3; tying IPRG to SGND

selects A = 2/3. The maximum value of V

ITH

is typically

about 1.98V, so the maximum sense voltage allowed across

the main N-channel MOSFET is 122mV, 202mV, or 82mV

for the three respective states of the IPRG pin. The peak

sense voltages for the two controllers can be independently

selected by the IPRG1 and IPRG2 pins.

However, once the controller’s duty cycle exceeds 20%,

slope compensation begins and effectively reduces the

peak sense voltage by a scale factor given by the curve

in Figure 1.

The peak inductor current is determined by the peak

sense voltage and the on-resistance of the main N-chan-

nel MOSFET:

V

SENSE(MAX)

DS(ON)

Power-Good (PGOOD) Pin

A window comparator monitors both feedback voltages

and the open-drain PGOOD output pin is pulled low when

either or both feedback voltages are not within ±10% of the

0.6V reference voltage. PGOOD is low when the LTC3836

is shut down or in undervoltage lockout.

2-Phase Operation

Why the need for 2-phase operation? Many constant-fre-

quency dual switching regulators operate both controllers

in phase (i.e., single phase operation). This means that

both topside MOSFETs are turned on at the same time,

causing current pulses of up to twice the amplitude of

those from a single regulator to be drawn from the input

capacitor. These large amplitude pulses increase the total

RMS current ﬂ owing in the input capacitor, requiring the

use of larger and more expensive input capacitors, and

increase both EMI and power losses in the input capacitor

and input power supply.

With 2-phase operation, the two controllers of the LTC3836

are operated 180 degrees out-of-phase. This effectively

interleaves the current pulses coming from the topside

MOSFET switches, greatly reducing the time where they

overlap and add together. The result is a signiﬁ cant reduc-

tion in the total RMS current, which in turn allows the

use of smaller, less expensive input capacitors, reduces

shielding requirements for EMI and improves real world

operating efﬁ ciency.

DUTY CYCLE (%)

SF = I/I

MAX

(%)

110

100

37362 F01

200

100

Figure 1. Maximum Peak Current vs Duty Cycle

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LTC3836EGN#PBF

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Description:

Switching Voltage Regulators Low Input Voltage 2-Phase Synch Controller w/ Tracking

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