LTC3836
19
3836fb
APPLICATIONS INFORMATION
For coincident tracking,
t
SS2
= t
SS1
V
OUT2F
V
OUT1F
where V
OUT1F
and V
OUT2F
are the fi nal, regulated values
of V
OUT1
and V
OUT2
. V
OUT1
should always be greater than
V
OUT2
when using the TRACK/SS2 pin for tracking. If no
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
to fi nal regulated output voltage.
Phase-Locked Loop and Frequency Synchronization
The LTC3836 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the main N-channel
MOSFET of controller 1 to be locked to the rising edge
of an external clock signal applied to the SYNC/FCB pin.
The turn-on of controller 2’s main N-channel MOSFET is
thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external fi lter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specifi ed in the Electrical
Characteristics table. Note that the LTC3836 can only be
synchronized to an external clock whose frequency is within
range of the LTC3836’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature
and variations, to be between 300kHz and 750kHz. A
simplifi ed block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillators frequency, f
OSC
, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
PLLLPF PIN VOLTAGE (V)
0
0
FREQUENCY (kHz)
0.5 1 1.5 2
3836 F08
2.4
200
400
600
800
1000
1200
1400
Figure 8. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
Figure 9. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3836 F09
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
FCB
LTC3836
20
3836fb
APPLICATIONS INFORMATION
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor C
LP
holds the voltage.
The loop fi lter components, C
LP
and R
LP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The fi lter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01μF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Table 1.
PLLLPF PIN SYNC/FCB PIN FREQUENCY
0V DC Voltage 300kHz
Floating DC Voltage 550kHz
V
IN
DC Voltage 750kHz
RC Loop Filter Clock Signal Phase-Locked to External Clock
5V supply is available. Note that in applications where the
supply voltage to C
B
exceeds V
IN
, the BOOST pin will draw
approximately 500μA in shutdown mode.
Table 2 summarizes the different states in which the
SYNC/FCB pin can be used
Table 2.
SYNC/FCB PIN CONDITION
0V to 0.5V Forced Continuous Mode
Current Reversal Allowed
0.7V to V
IN
Pulse-Skipping Operation Enabled
No Current Reversal Allowed
External Clock Signal Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Figure 11. Foldback Current Limiting
Topside MOSFET Drive Supply (C
B
, D
B
)
In the Functional Diagram, external bootstrap capaci-
tor C
B
is charged from a boost power source (usually
V
IN
) through diode D
B
when the SW node is low. When
a MOSFET is to be turned on, the C
B
voltage is applied
across the gate-source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
the input supply. V
BOOST
= 2V
IN
. C
B
must be 100 times the
total input capacitance of the topside MOSFET. The reverse
breakdown of D
B
must be greater than V
IN(MAX)
. Figure 6
shows how a 5V gate drive can be achieved if a secondary
Fault Condition: Short-Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the cur-
rent in proportion to the severity of the fault.
Foldback current limiting is implemented by adding
diodes D
FB1
and D
FB2
between the output and the I
TH
pin as shown in Figure 11. In a hard short (V
OUT
= 0V),
the current will be reduced to approximately 50% of the
maximum output current.
+
1/2 LTC3836
V
FB
I
TH
R2
D
FB1
V
OUT
D
FB2
3836 F11
R1
LTC3836
21
3836fb
APPLICATIONS INFORMATION
Using a Sense Resistor
A sense resistor R
SENSE
can be connected between V
IN
and SW to sense the output load current. In this case, the
drain of the topside N-channel MOSFET is connected to
SENSE
pin and the source is connected to the SW pin of
the LTC3836. Therefore, the current comparator monitors
the voltage developed across R
SENSE
, not the V
DS
of the
top MOSFET. The output current that the LTC3836 can
provide in this case is given by:
I
OUT(MAX)
=
V
SENSE(MAX)
R
DS(ON)
I
RIPPLE
2
Setting ripple current as 40% of I
OUT(MAX)
and using
Figure 1 to choose SF, the value of R
SENSE
is:
R
SENSE
=
5
6
•SF
V
SENSE(MAX)
I
OUT(MAX)
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of an external
MOSFET. Therefore the load current is well controlled with
a sense resistor. However the sense resistor causes extra
I
2
R losses in addition to those of the MOSFET. Therefore,
using a sense resistor lowers the effi ciency of LTC3836,
especially at high load currents.
Low Supply Operation
Although the LTC3836 can function down to below 2.4V,
the maximum allowable output current is reduced as
V
IN
decreases below 3V. Figure 12 shows the amount of
change as the supply is reduced down to 2.4V. Also
shown is the effect on V
REF
.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest amount of time
that the LTC3836 is capable of turning the main N-chan-
nel MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle and high frequency applica-
tions may approach the minimum on-time limit and care
should be taken to ensure that:
t
ON(MIN)
<
V
OUT
f
OSC
•V
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3836 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3836 is typically about 200ns. However,
as the peak sense voltage (I
L(PEAK)
• R
DS(ON)
) decreases,
the minimum on-time gradually increases up to about
250ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuous mode is selected and the duty cycle falls below
the minimum on-time requirement, the output will be
regulated by overvoltage protection.
Figure 12. Line Regulation of V
REF
and
Maximum Sense Voltage for Low Input Supply
INPUT VOLTAGE (V)
75
NORMALIZED VOLTAGE OR CURRENT (%)
85
95
105
80
90
100
2.2 2.4 2.6 2.8
3836 F12
3.02.12.0 2.3 2.5 2.7 2.9
V
REF
MAXIMUM
SENSE VOLTAGE

LTC3836EGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low Input Voltage 2-Phase Synch Controller w/ Tracking
Lifecycle:
New from this manufacturer.
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