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MC88915TFN55

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10
MOTOROLA
MC88915TFN160
SYNC INPUT TIMING REQUIREMENTS
Symbol Parameter Minimum Maximum Unit
t
RISE/FALL
,SYNC Inputs Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V — 3.0 ns
t
CYCLE
, SYNC Inputs Input Clock Period SYNC Inputs 12.5 100 ns
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs 50% ±25%
1. These t
CYCLE
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T
A
=0° C to +70° C, V
CC
= 5.0 V ± 5%
Symbol
Parameter Test Conditions
V
CC
V
Target Limit Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V 4.75
5.25
2.0
2.0
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V 4.75
5.25
0.8
0.8
V
V
OH
Minimum High–Level Output
Voltage
V
in
= V
IH
or V
IL
I
OH
= –36 mA
1
4.75
5.25
4.01
4.51
V
V
OL
Maximum Low–Level Output
Voltage
V
in
= V
IH
or V
IL
I
OL
= 36 mA
1
4.75
5.25
0.44
0.44
V
I
in
Maximum Input Leakage Current V
I
= V
CC
or GND 5.25 ±1.0 µA
I
CCT
Maximum I
CC
/Input V
I
= V
CC
– 2.1 V 5.25
2.0
2
mA
I
OLD
Minimum Dynamic Output Current
3
V
OLD
= 1.0V Max 5.25 88 mA
I
OHD
V
OHD
= 3.85V Min 5.25 –88 mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
I
= V
CC
or GND 5.25 1.0 mA
I
OZ
Maximum 3–State Leakage Current V
I
= V
IH
or V
IL
;V
O
= V
CC
or GND 5.25 ±50
4
µA
1. I
OL
and I
OH
are 12mA and –12mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I
OZ
is preliminary, will be finalized upon ‘MC’ status.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol Parameter Typical Values Unit Conditions
C
IN
Input Capacitance 4.5 pF V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance 40 pF V
CC
= 5.0 V
PD
1
Power Dissipation @ 50MHz with 50Ω Thevenin Termination 15mW/Output
120mW/Device
mW V
CC
= 5.0 V
T = 25°C
PD
2
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND 57mW/Output
456mW/Device
mW V
CC
= 5.0 V
T = 25° C
NOTE: PD
1
and PD
2
mW/Output numbers are for a ‘Q’ output.
FREQUENCY SPECIFICATIONS (T
A
=0° C to +70° C, V
CC
= 5.0 V ±5%)
Guaranteed Minimum
Symbol Parameter TFN160 Unit
f
max
1
Maximum Operating Frequency (2X_Q Output) 160 MHz
Maximum Operating Frequency (Q0–Q4,Q5 Output) 80 MHz
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V
CC
/2.
11
MOTOROLA
MC88915TFN160 (continued)
AC CHARACTERISTICS (T
A
=0° C to +70° C, V
CC
= 5.0V ±5%, Load = 50Ω Terminated to V
CC
/2)
Symbol
Parameter Min Max Unit Condition
t
RISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2V
CC
and 0.8V
CC
)
1.0 2.5 ns Into a 50Ω Load
Terminated to V
CC
/2
t
RISE/FALL
2X_Q Output
Rise/Fall Time 0.5 1.6 ns t
RISE
: 0.8V – 2.0V
t
FALL
: 2.0V – 0.8V
t
PULSE
WIDTH
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5
, Q/2 @ V
CC
/2
0.5t
CYCLE
– 0.5
2
0.5t
CYCLE
+ 0.5
2
ns Into a 50Ω Load
Terminated to V
CC
/2
t
PULSE
WIDTH
(2X_Q Output)
Output Pulse Width: 80MHz
2X_Q @ V
CC
100MHz
133MHz
160MHz
0.5t
CYCLE
– 0.7
0.5t
CYCLE
– 0.5
0.5t
CYCLE
– 0.5
TBD
0.5t
CYCLE
+ 0.7
0.5t
CYCLE
+ 0.5
0.5t
CYCLE
+ 0.5
TBD
ns
t
PD
1
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
(With 1MΩ from RC1 to An V
CC
)
ns See Note 2 and
Figure 2 for Detailed
SYNC
Feedback
(Measured
at
SYNC0
or
1
and
FEEDBACK Input Pins)
133MHz
160MHz
–1.05
–0.9
–0.25
–0.10
Figure
2
for
Detailed
Explanation
t
CYCLE
(2x_Q Output)
Cycle–to–Cycle Variation 133MHz
160MHz
t
CYCLE
– 300ps
t
CYCLE
– 300ps
t
CYCLE
+ 300ps
t
CYCLE
+ 300ps
t
SKEWr
3
(Rising) See Note 4
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
— 500 ps All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
t
SKEWf
3
(Falling)
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
— 500 ps All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
t
SKEWall
3
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5
Falling
— 750 ps All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
t
LOCK
4
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0 10 ms Also Time to LOCK
Indicator High
t
PZL
5
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5
, and Q/2
3.0 14 ns Measured With the
PLL_EN Pin Low
t
PHZ
,t
PLZ
5
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5
, and Q/2
3.0 14 ns Measured With the
PLL_EN Pin Low
1. T
CYCLE
in this spec is 1/Frequency at which the particular output is running.
2. The T
PD
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With V
CC
fully powered–on, and an output properly connected to the FEEDBACK pin. t
LOCK
maximum is with C1 = 0.1µF, t
LOCK
minimum is with
C1 = 0.01µF.
5. The t
PZL
, t
PHZ
, t
PLZ
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
12
MOTOROLA
Applications Information for All Versions
General AC Specification Notes
1. Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase–locked
operation. It is not possible to have the part in phase–lock
on ATE (automated test equipment). Statistical
characterization techniques were used to guarantee those
specifications which cannot be measured on the ATE.
MC88915TFN55, 70 and 100 units were fabricated with
key transistor properties intentionally varied to create a 14
cell designed experimental matrix. IC performance was
characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area, to set
performance limits of ATE testable specifications within
those which are to be guaranteed by statistical
characterization. In this way all units passing the ATE test
will meet or exceed the non–tested specifications limits.
2. These two specs (t
RlSE/FALL
and t
PULSE
Width 2X_Q
output) guarantee that the MC88915T meets the 40MHz
and 33MHz MC68040 P–Clock input specification (at
80MHz and 66MHz, respectively). For these two specs to
be guaranteed by Motorola, the termination scheme
shown below in Figure 1 must be used.
3. The wiring Diagrams and explanations in Figure 5
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5
output, thus creating a 180°
phase shift between the SYNC input and the “Q” outputs.
Table 1 below summarizes the allowable SYNC frequency
range for each possible configuration.



 



Ω
Figure 1. MC68040 P–Clock Input Termination Scheme
R
p
= 1.5 Z
o
R
p
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
Corresponding VCO
Frequency Range
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
HIGH Q/2 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) 0°
HIGH Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 0°
HIGH Q5 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 180°
HIGH 2X_Q 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 0°
LOW Q/2 2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec) 0°
LOW Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) 0°
LOW Q5 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAXSpec) 180°
LOW 2X_Q 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAXSpec) 0°
4. A 1MΩ resistor tied to either Analog V
CC
or Analog GND as
shown in Figure 2 is required to ensure no jitter is present
on the MC88915T outputs. This technique causes a phase
offset between the SYNC input and the output connected
to the FEEDBACK input, measured at the input pins. The
t
PD
spec describes how this offset varies with process,
temperature, and voltage. The specs were arrived at by
measuring the phase relationship for the 14 lots described
in note 1 while the part was in phase–locked operation.
The actual measurements were made with a 10MHz
SYNC input (1.0ns edge rate from 0.8V – 2.0V) with the
Q/2 output fed back. The phase measurements were
made at 1.5V. The Q/2 output was terminated at the
FEEDBACK input with 100Ω to V
CC
and 100Ω to ground.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MC88915TFN55

Mfr. #:
Buy MC88915TFN55
Manufacturer:
NXP Semiconductors
Description:
IC DRIVER CLK PLL 55MHZ 28-PLCC
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