R1LV0208BSA
R10DS0050EJ0100 Rev.1.00 Page 12 of
13
2011.03.30
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*2
V
CC
for data retention V
DR
2.0 - 3.6 V
Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
- 1
*1
2 μA ~+25°C
- - 3 μA ~+40°C
- - 8 μA ~+70°C
Data retention current I
CCDR
- - 10 μA ~+85°C
Vcc=3.0V, Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
Chip deselect to data retention time t
CDR
0 - - ns
Operation recovery time t
R
5 - - ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
